ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen · IRC meetings each Monday at 1800 UTC · next meeting TBD
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<d1b2> <dub_dub_11> update: I need to remember that xdr=1 and xdr=0 are in fact different (doh)
<d1b2> <dub_dub_11> a registered output with no clock provided is a great way to "optimise" your design 🙃
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<_whitenotifier> [nmigen] whitequark commented on issue #562: Way to start register with "random" value? - https://git.io/JL0Gc
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<_whitenotifier> [nmigen] cestrauss opened issue #564: cxxsim: directly initializing memory - https://git.io/JLzt6
<_whitenotifier> [nmigen] cestrauss opened issue #565: cxxsim: random garbage in memory traces - https://git.io/JLztd
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