00:56 <_whitenotifier> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JLM9v

00:56 <_whitenotifier> [YoWASP/yosys] whitequark e14ef31 - Update dependencies.

20:30 <_whitenotifier> [nmigen] cestrauss opened issue #568: cxxsim: error when reading unused combinatorial signal - https://git.io/JLytj

21:19 <korken89> Hi all, I'm bringing up an ECP5 board which has its clock directly connected to a dedicated PLL input pin (LRC_GPLLOT_IN), hence I need to instantiate a PLL to provide the system with a system clock. Greping around in the nmigen code I am unable to find how to instantiate a PLL, is there anyone here that has done this?

21:50 <d1b2> <dub_dub_11> you need to generate the Verilog core and Instance it

21:54 <korken89> Hmm, that's unfortunate - I'd like to find a way using nmigen. I found this PR (and related issue): https://github.com/nmigen/nmigen/pull/426 , I wonder if the code in the PR is usable. I've never used the `Instance` before, so this will be interesting :)

22:13 <d1b2> <dub_dub_11> PLLs in nMigen is a WIP

22:13 <d1b2> <dub_dub_11> as you have found yeah

22:18 <vup> using `Instance` should work

22:18 <smkz> is there an idiomatic/recommended way to determine at compile-time the necessary width of a signal based on the largest value it can have (like, doing a log 2)

22:21 <Sarayan> Doesn't nmigen do that automatically when you tell it the range of values instead of a number of bits?

22:22 <agg> korken89: if you haven't got it already, https://dpaste.com/BFBTW533B might be useful

22:22 <agg> smkz: s = Signal(range(1000)) will make a ten-bit signal for example

22:23 <smkz> agg: perfect, thank you

22:23 <agg> korken89: you can use `ecppll` (part of prjtrellis) or lattice diamond to generate the relevant configuration attributes/parameters

22:27 <agg> and the lattice document "FPGA Libraries Reference Guide" contains all available attributes/params/ports for all the ECP5 primitives

22:37 <RaYmAn> korken89: kbeckmann also has this possibly slightly WIP module https://github.com/kbeckmann/pergola_projects/blob/master/pergola/util/ecp5pll.py (I think there wa

22:38 <RaYmAn> err

22:38 <RaYmAn> it's similar to the one you posted though.

22:41 <korken89> Thanks! Seems like for a simple static config this should work fine :)

22:50 <kbeckmann> that python code is just my attempt at porting the ecp5pll c++ code to python

22:51 <kbeckmann> it might be subtly wrong as i don't quite understand what it's doing, i just ported it. but it works!

22:51 <korken89> :D