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<
_whitenotifier >
[YoWASP/nextpnr] whitequark c6bdad5 - Update dependencies.
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<
_whitenotifier >
[YoWASP/yosys] whitequark 8ce9ccd - Update dependencies.
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<
rodrigomelo9 >
Copyright (C) 2020 whitequark`` and in the second one ```Copyright (C) 2019-2020 whitequark
11:20
<
rodrigomelo9 >
Copyright (C) 2011-2019 M-Labs Limited```.
11:23
<
d1b2 >
<DX-MON> the m-labs one is do not use, the nmigen org one is the correct and official one
11:23
<
d1b2 >
<DX-MON> it's better to not dive into that subject further.. just.. don't use the m-labs one
11:24
<
rodrigomelo9 >
Is ok, I got it.
11:24
<
rodrigomelo9 >
Thanks
11:36
<
d1b2 >
<dub_dub_11> Also, star the nMigen repo so Google eventually starts showing people the right one...
11:40
<
rodrigomelo9 >
Already done ;-)
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<
_whitenotifier >
[nmigen] github-4o commented on issue #363: Can I create an active-low (asynchronous) reset? -
https://git.io/JtCPA
12:44
<
_whitenotifier >
[nmigen] github-4o edited a comment on issue #363: Can I create an active-low (asynchronous) reset? -
https://git.io/JtCPA
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<
_whitenotifier >
[nmigen] github-4o commented on issue #363: Can I create an active-low (asynchronous) reset? -
https://git.io/JtC9U
14:18
<
_whitenotifier >
[nmigen] github-4o edited a comment on issue #363: Can I create an active-low (asynchronous) reset? -
https://git.io/JtC9U
14:18
<
_whitenotifier >
[nmigen] github-4o edited a comment on issue #363: Can I create an active-low (asynchronous) reset? -
https://git.io/JtC9U
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<
_whitenotifier >
[nmigen] github-4o edited a comment on issue #363: Can I create an active-low (asynchronous) reset? -
https://git.io/JtC9U
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<
_whitenotifier >
[nmigen] github-4o commented on issue #363: Can I create an active-low (asynchronous) reset? -
https://git.io/JtCxS
16:47
<
_whitenotifier >
[nmigen] github-4o edited a comment on issue #363: Can I create an active-low (asynchronous) reset? -
https://git.io/JtCxS
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<
_whitenotifier >
[nmigen] github-4o edited a comment on issue #363: Can I create an active-low (asynchronous) reset? -
https://git.io/JtC9U
17:14
<
_whitenotifier >
[nmigen] github-4o edited a comment on issue #363: Can I create an active-low (asynchronous) reset? -
https://git.io/JtCxS
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<
_whitenotifier >
[nmigen] github-4o edited a comment on issue #363: Can I create an active-low (asynchronous) reset? -
https://git.io/JtCxS
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<
_whitenotifier >
[nmigen] whitequark commented on issue #363: Can I create an active-low (asynchronous) reset? -
https://git.io/JtWUY
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<
_whitenotifier >
[YoWASP/yosys] whitequark 5e121bd - Update dependencies.
18:46
<
_whitenotifier >
[YoWASP/yosys] whitequark 0aba9d4 - Update wasi-sdk.
18:46
<
_whitenotifier >
[YoWASP/yosys] whitequark 7ea13ee - Update dependencies.
18:46
<
_whitenotifier >
[YoWASP/yosys] ... and 10 more commits.
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<
_whitenotifier >
[nmigen] nickoe opened pull request #584: Fixup symbiflow toolchain for xilinx 7series -
https://git.io/JtWqJ
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<
_whitenotifier >
[nmigen] nickoe synchronize pull request #584: Fixup symbiflow toolchain for xilinx 7series -
https://git.io/JtWqJ
20:14
<
_whitenotifier >
[nmigen] codecov[bot] commented on pull request #584: Fixup symbiflow toolchain for xilinx 7series -
https://git.io/JtWmZ
20:14
<
_whitenotifier >
[nmigen] codecov[bot] edited a comment on pull request #584: Fixup symbiflow toolchain for xilinx 7series -
https://git.io/JtWmZ
20:14
<
_whitenotifier >
[nmigen] codecov[bot] edited a comment on pull request #584: Fixup symbiflow toolchain for xilinx 7series -
https://git.io/JtWmZ
20:15
<
_whitenotifier >
[nmigen] codecov[bot] edited a comment on pull request #584: Fixup symbiflow toolchain for xilinx 7series -
https://git.io/JtWmZ
20:19
<
_whitenotifier >
[nmigen] nickoe edited pull request #584: Fixup symbiflow toolchain for xilinx 7series -
https://git.io/JtWqJ
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<
d1b2 >
<benzn> just a friendly note that nmigen has been mindblowingly great for a lot of hardware work/research i've been doing
21:15
<
d1b2 >
<benzn> i.e. using numpy to generate bram init contents on the fly for RF work reduces the dev/test feedback loop to basically zero
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<
d1b2 >
<benzn> or solving for PLL params on the fly
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<
d1b2 >
<benzn> it's great. thanks for all the hard work 🙏
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<
d1b2 >
<mubes> Can someone tell me how I can build one module rather than a whole system? Specifically, I would like to integrate a luna-HS USB interface into an existing verilog design if that were possible...in the olden days I remember seeing stuff for migen about how to do it, but I can't even find that now 😕
22:48
<
agg >
from nmigen.back import verilog; verilog.convert(module, ports=[module.in, module.out, ...])
22:48
<
agg >
you'll need to put whichever ports you want accessible on the resulting verilog in ports there
22:49
<
d1b2 >
<mubes> thanks, I'll give it a try...I'm not expecting this to be easy 🙂
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<
d1b2 >
<mubes> I guess the alternative would be to bring the Verilog into nmigen...is there an equivalent incantation for incorporating an existing verilog module by any chance? Trying to figure out how best to eat this elephant...
22:57
<
Lofty >
mubes: Instance is the tool for that
22:58
<
d1b2 >
<mubes> Thanks, I can probably find my way now, ta
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