ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen · IRC meetings each Monday at 1800 UTC · next meeting TBD
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<agg> mubes: when you call platform.request("resource_name"), you can specify xdr=2 to get a DDR object
<d1b2> <mubes> So I just create a resource with those four pins in, do a request to get them, and send the result into get_input?
<agg> you don't need to call get_input
<agg> sorry, was about to type an example but
<d1b2> <mubes> :-)
<agg> do you want to clock the DDR with the clock on pin 0?
<agg> or with the FPGA's clock?
<d1b2> <mubes> Yes.
<agg> ok
<d1b2> <mubes> The design already works in 'clean' verilog, but nmigen gives me more flexibility so trying to move it over. How do 'connectors' figure in all this?
<agg> so in your platform you might have something like Resource("pmod", 0, Subsignal("clk", Pins("A1", dir="i")), Subsignal("dat", Pins("A2 A3 A4 A5", dir="i")))
<agg> and then in your design, pmod = platform.request("pmod", 0, xdr=2)
<_whitenotifier> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JtlPG
<_whitenotifier> [YoWASP/nextpnr] whitequark 0b27572 - Update dependencies.
<d1b2> <mubes> Oh great, I can define it all in one then! Brilliant....and so simple, once you know :-))
<agg> and to use it, m.d.comb += pmod.dat.i_clk.eq(pmod.clk.i), your_thing.dat_a = pmod.dat.i0, your_thing.dat_b = pmod.dat.i1
<agg> hmmm
<agg> sorry, let me rephrase that first bit
<agg> pmod = platform.request("pmod", 0, xdr = {"dat": 2})
<agg> you don't want the clk to be a ddr input, after all
<vup> @mubes: connectors can not be used directly, they can be seen as a way to rename / reorder pins which then can be used in Resource definitions. Say for example you have a `Connector("pmod", 0, "B0 B1 B2 B3 - -")`. Then you can write `Pins("1 2 3", conn=("pmod", 0))` to get the equivalent of `Pins("B0 B1 B2")`
<d1b2> <mubes> Nope. Eventually I want to push it through a delay block, but one hill at a time.
<agg> usually to use the connector it's as vup says, but you can call platform.add_resources([Resource("bla", 0, Pins("0 1 2 3", conn=("pmod", 0))])
<d1b2> <mubes> @vup ok, that makes sense...I wondered why I couldn't reach them.
<agg> and you can call that inside your code, rather than in your platform file
<agg> so it lets the platform be more generic, and your top-level code can decide what to do with them
<d1b2> <mubes> Thanks guys...enough clues to keep going for a bit longer!
<agg> (you can also write Pins("pmod_0:0 pmod_0:1") etc but idk why you would
<vup> (in that example you would call platform.add_resources(platform.break_off_pmod) yourself, like done here: https://github.com/nmigen/nmigen-boards/blob/5c8c8ca2e7c0a4eb5bc09c2f30eea94b024c17a0/nmigen_boards/icebreaker.py#L74)
<agg> the xdr argument to platform.request either takes a number 0/1/2/etc which applies to all signals, or a dictionary of subsignal names to numbers
<d1b2> <mubes> Strewth, there's a lot of layered complexity in here...
<agg> with xdr=0 your object has .i or .o or .oe (depending on dir), xdr=1 gets i_clk and o_clk in addition, and xdr=2 gets i0/i1/o0/o1, etc
<vup> (also you can of course nest connectors for more confusion :P (they can take a `conn=...` argument aswell))
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<d1b2> <mubes> Turtles all the way down.
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<d1b2> <mubes> I'm gonna end up reading the output verilog just to see if I managed to do what I think I managed to do!
<d1b2> <mubes> Thanks everyone. I'll do battle on this tomorrow. Gnight.
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<_whitenotifier> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/Jtl1c
<_whitenotifier> [YoWASP/yosys] whitequark fab1c12 - Update dependencies.
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<_whitenotifier> [nmigen] BracketMaster commented on issue #583: Unusual Display Behaviors - https://git.io/JtlS3
<_whitenotifier> [nmigen] BracketMaster closed issue #583: Unusual Display Behaviors - https://git.io/JtWeR
<_whitenotifier> [nmigen] whitequark commented on issue #583: Unusual Display Behaviors - https://git.io/JtlS4
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<_whitenotifier> [nmigen-boards] whitequark reviewed pull request #137 commit - https://git.io/Jtl9J
<_whitenotifier> [nmigen-boards] whitequark reviewed pull request #137 commit - https://git.io/Jtl9k
<_whitenotifier> [nmigen-boards] whitequark reviewed pull request #137 commit - https://git.io/Jtl9I
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<_whitenotifier> [nmigen] nickoe edited a comment on pull request #584: Fixup symbiflow toolchain for xilinx 7series - https://git.io/JtWjM
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<pftbest> Hello. Does anyone know why someone would use SSTL135 iotype for DDR3 while having 1.5 volts on VCCIO?
<pftbest> I've looked at some docs from Lattice and it seems maximum allowed VCCIO is 1.42v for SSTL135
<pftbest> But at the same time, their DDR3 example project for Versa board is using SSTL135 and has 1.5 on VCCIO
<pftbest> I'm asking this because nmigen-boards for ECIX-5 is using SSTL135 but the litex-boards is using SSTL15
<pftbest> for the same pins and I have no idea which is correct
<whitequark> cc daveshah
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