<modwizcode>
That bothred me when I was writing code there's like 3 ways to get the width and they feel redundent (and some of the code uses more than one way in similar code. I think the fifo code has both len() and width?)
<agg>
ktemkin: do you want to file a pr fix or shall I?
<ktemkin>
I'll PR one real quick.
<_whitenotifier>
[nmigen] ktemkin opened pull request #582: vendor.lattice_ecp5: correctly generate OE signaling when xdr=0 - https://git.io/JtnGO
<agg>
conceivably you could do that repl once and use it in all the other xdrs too, with get_oreg instead of get_oereg
<_whitenotifier>
[nmigen] codecov[bot] commented on pull request #582: vendor.lattice_ecp5: correctly generate OE signaling when xdr=0 - https://git.io/JtnGR
<_whitenotifier>
[nmigen] codecov[bot] edited a comment on pull request #582: vendor.lattice_ecp5: correctly generate OE signaling when xdr=0 - https://git.io/JtnGR
<_whitenotifier>
[nmigen] codecov[bot] edited a comment on pull request #582: vendor.lattice_ecp5: correctly generate OE signaling when xdr=0 - https://git.io/JtnGR
<_whitenotifier>
[nmigen] codecov[bot] edited a comment on pull request #582: vendor.lattice_ecp5: correctly generate OE signaling when xdr=0 - https://git.io/JtnGR
nengel has quit [Quit: gone afk]
emeb_mac has joined #nmigen
nengel has joined #nmigen
cr1901_modern has quit [Ping timeout: 264 seconds]
cr1901_modern has joined #nmigen
nengel has quit [Quit: gone afk]
nengel has joined #nmigen
nengel has quit [Quit: gone afk]
pftbest has quit [Remote host closed the connection]
pftbest has joined #nmigen
cr1901_modern has quit [Quit: Leaving.]
cr1901_modern has joined #nmigen
<d1b2>
<twam> I encountered some problem using word_select/bit_select.My understanding is that word_select(x,y) should be the same as bit_select(x*y, y) , but when I use the former my design compiles and the latter fails with some IndexError: Cannot stop slice 33 bits into 32-bit value error.
<d1b2>
<twam> Interestingly this only seems to be a problem when building for my Icebreaker board. In the simulator I don't have this issue.
Bertl is now known as Bertl_oO
<vup>
@twam can you provide a file that exhibits this problem?
chipmuenk has quit [Quit: chipmuenk]
<d1b2>
<twam> This is the current https://gist.github.com/twam/51733f6ae1c9fd7f53bd5ab05060b410 file. I also don't understand why counter needs to Signal(5) to work with word_select on hardware. In simulation a Signal(number_of_digits) works and is what I would expect.
<d1b2>
<twam> Looks like updating to latest nmigen and yosys solved the issue.
<d1b2>
<twam> That's why I also found while googling, and there I though updating might help. I was on an quite old version as many tutorials still link to the old github repo 😦
<vup>
ah yeah
<d1b2>
<twam> How can I overwrite the default clock of a module? Something like def __init__(self): self.clk = Signal() def elaborate(): m = Module() m.d.sync.clk = self.clk return m doesn't seem to work.
<vup>
@twam if you want to change the clock a existing module is using, you can use `DomainRenamer("new_clk")(TheModule())`
<vup>
otherwise you can add a new ClockDomain to your Module using `m.domains += ClockDomain("the_name")` and then drive the clock of that domain using `m.d.comb += ClockSignal("the_name").eq(your_source)`
<vup>
finally you can start using the clock domain using `m.d.the_name += a.eq(b)`
<d1b2>
<twam> I wrote a small module to read out an ADC via SPI. This module requires a clock which is ~1/4 of my main clock. What's the suggested way to supply this slower clock to the module without touching it?
<vup>
@twam DomainRenamer
<d1b2>
<twam> Thanks. I'll check that out!
jeanthom has quit [Ping timeout: 240 seconds]
<pftbest>
TIL why it's good to have add_preferences="SYSCONFIG MASTER_SPI_PORT=ENABLE;"
key2 has quit [Read error: Connection reset by peer]
key2 has joined #nmigen
sorear has quit [Ping timeout: 265 seconds]
sorear has joined #nmigen
pftbest has quit [Remote host closed the connection]
pftbest has joined #nmigen
<awygle>
lsneff: do you have a rough roadmap for ligeia? some idea of the things you'd like to do and a rough ordering?