00:24 <agg> mubes: you'll want platform.add_file("path/to/file.v") to include the verilog in the build, and then inst = m.submodules.inst = Instance("INSTANCE_NAME", p_PARAM=val, a_ATTRIB=val, i_INPUT=signal, o_OUTPUT_signal) to wire it up

00:26 <d1b2> <mubes> perfect, thank you. Is this stuff documented anywhere? I looked in nmigen/hdl/ir.py but there's not so much in the way of docs in there....don't want to be hassling here if I can pick the stuff up online somewhere.

00:29 <agg> there's examples/basic/inst.py but it doesn't have add_file

00:36 <d1b2> <mubes> ta

00:37 <d1b2> <mubes> I think that's where I'd got stuck, couldn't see how to pull in the code itself.

00:38 <agg> if you have an existing large verilog build that's already all set up, and you just want luna usb, it seems like exporting luna as verilog and using that in your build will be simplest, at a guess

00:38 <agg> just because otherwise you need to get an nmigen build set up, but if you don't have that much verilog or if your board is a dev board in nmigen-boards that might be pretty quick.

00:39 <agg> (that said, if you're interested in doing things in nmigen it's well worth getting the build set up there instead i would say)

00:47 <d1b2> <mubes> I think I'm going to head the integrate-into-nmigen route for ease...eventually I'll want a soc in there too. I have both nmigen and verilog builds up and running so this is exactly the fork in the path point.

12:45 <_whitenotifier> [nmigen] nickoe commented on pull request #584: Fixup symbiflow toolchain for xilinx 7series - https://git.io/JtWjM

17:52 <nickoe> mmm, anyone who know what to put in the template for this comment? https://github.com/SymbiFlow/symbiflow-examples/issues/123#issuecomment-769025271

19:16 <nickoe> ok, I sorta fixed that, but I am having problems with the flashing code using the correct path to the bit file..

19:27 <_whitenotifier> [nmigen] nickoe edited pull request #584: Fixup symbiflow toolchain for xilinx 7series - https://git.io/JtWqJ

19:28 <_whitenotifier> [nmigen] nickoe commented on pull request #584: Fixup symbiflow toolchain for xilinx 7series - https://git.io/JtlE0

19:39 <esden> nickoe: o/ :)

20:10 <nickoe> esden: I was just watching your "let me poke with nmigen" the other day :) But I tried to use symbiflow for the artix7, but not yet quite mmm, working. I have some issues with the flashing stuff not using the correct path to the bin file.

23:43 <d1b2> <mubes> Folks, sorry to trouble again, but I'm finding all of this quite hard going, still on the cliff-face I guess. I've now managed to get my verilog integrated with nmigen, but I need to feed it with DDR inputs. These are on a PMOD (bits 1..4, clk on bit 0). I can see that the correct modules are called up via get_input down to get_iddr which instantiates a IDDRX1F for each bit, but for the life of me I can't figure out what I'm supposed to have in my

23:43 <d1b2> platform resources to trigger all of that magic to happen..indeed, I've defined by pmod's as Resources cos I can't see how to access them as connectors at all. Can someone please help me out or point me at some doc or examples?