<zignig>
tpw_rules: most of my work has been based on your investigations.
<zignig>
trying to unspecify the interfaces mostly ;))
<zignig>
I have managed to get a number of constructs defined, the idea is to make a "get started" construct for any nmigen-board.
<zignig>
blinky --> 16 bit awesome core --> galactiv domination...
* zignig
's fingers are failing G'nite all. back tommorrow.
<lkcl>
night
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<d1b2>
<OmniTechnoMancer> I am attempting to 6502, it is... interesting, I am probably making a huge mess for myself (at least I wont have to do decimal mode)
<GenTooMan>
zignig galactic domination might be difficult, too much competition for that.
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<d1b2>
<benzn> i might be doing this wrong but: with the vivado backend I'm trying to set up SERDES blocks and I need to constrain the input/output pads to specific locations otherwise everything will be optimized out
<agg>
benzn: are you using dir=”-” in platform.request?
<agg>
Evidlo: that's a classic nmigen usage error, the ports argument needs to be an iterable like a list or tuple, but in that line (top.led) is just brackets, it should be (top.led,) or [top.led]
<agg>
benzn: dir="i" or o or io or oe will insert the relevant platform primitive for the io port (eg your IBUF), while "-" just gives you the raw top level signal directly, which is what you want if you're giving a pin to a platform primitive
<Evidlo>
I see, thanks
<d1b2>
<benzn> > TypeError: Direction must be one of "i", "o", "oe", or "io", not '-'
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<agg>
benzn: this should be in platform.request() not the platform class itself
<agg>
Evidlo: I think that specific issue in that tutorial has caused a lot of people that problem so it's been mentioned in this channel a few times, I thought nmigen had even added a specific diagnostic for it but I might be misremembering or maybe it didn't merge yet
<agg>
Really easy to do because with two signals you'd have (a, b) naturally so (a) seems ok
<agg>
Ah yea the simulator api changed a little
<d1b2>
<benzn> ah awesome, i think that worked. thanks!
<agg>
if you want a VCD file out, it's with simulator.write_vcd(path): simulator.run()
<agg>
if you're simulating combinatorial logic instead, simulator.add_process() instead of add_sync_process
<agg>
(and use simulator.run_until(time) instead of simulator.run())
<Evidlo>
can I still use nmigen.cli and do all this?
<agg>
I haven't used nmigen.cli and don't know how you'd give it the testbench function, but yes, its default 'simulate' action will run your design for a few clock cycles and output a vcd
<agg>
usually for a quick demo or test I'd just stick my own `if __name__ == "__main__"` at the bottom
<agg>
yes, I think nmigen.cli will just run your design for a few clock cycles, if you want a separate function to apply a stimulus you're probably beyond what nmigen.cli does for you, but the good news is it doesn't do much for you and it's easy to do yourself