ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen · IRC meetings each Monday at 1800 UTC · next meeting TBD
<_whitenotifier-5> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/Jtbqk
<_whitenotifier-5> [YoWASP/nextpnr] whitequark 9ab9c63 - Update dependencies.
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<_whitenotifier-5> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JtbmK
<_whitenotifier-5> [YoWASP/yosys] whitequark d1eb87c - Update dependencies.
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<d1b2> <OmniTechnoMancer> Yea pysim cannot, but afaik one of the points of having cxxsim is to be able to simulate mixed HDL
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<d1b2> <OmniTechnoMancer> I just ran into the no deep memories in pysim thing, and it unhelpfully manifests as an exit with no error message on windows apparently 😦
<d1b2> <OmniTechnoMancer> with python 3.9.1, so anyway time to work around that or use cxxrtl I guess
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<whitequark> you can extend the stack recursion depth
<whitequark> sys.setrecursionlimit()
<d1b2> <OmniTechnoMancer> does that help compile() exiting with no message?
<d1b2> <OmniTechnoMancer> no amount of setting the recursion limit makes a difference alas
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<d1b2> <OmniTechnoMancer> a depth of 17882 appears to the the last that works for me :/
<d1b2> <OmniTechnoMancer> so that appears to be the point at which the python compiler (assuming you turn the recursion limit up) crashes trying to compile an if with that many branches
<d1b2> <OmniTechnoMancer> time to use multiple memories instead
<whitequark> ohhhh right
<whitequark> that one is not affected by sys.setrecursionlimit
<whitequark> try uhhh
<whitequark> ulimit -s unlimited
<whitequark> or just some very large value. 128MB
<whitequark> (i don't quite recall what the syntax is)
<d1b2> <OmniTechnoMancer> I am on windows...
<whitequark> oh.
<d1b2> <OmniTechnoMancer> I will just use 3 0x4000 depth memories instead as this does not crash the python compiler
<whitequark> you could probably fix it with threading.stack_size()... but yeah
<d1b2> <OmniTechnoMancer> I wish to try cxxrtl but have been putting off the pain of determining how to build C++ properly
<d1b2> <OmniTechnoMancer> also of having to write the testbench driver in C++
<whitequark> cxxsim will take care of both once it works
<whitequark> but there's still some issues
<d1b2> <OmniTechnoMancer> indeed and I look forward to that but understand it is in progress
<d1b2> <OmniTechnoMancer> I suppose I could try hacking up a build
<d1b2> <OmniTechnoMancer> build_cxx that works for me to test current progress but probably just easier to use cxxrtl directly at this point
<d1b2> <OmniTechnoMancer> Thank you for all your work on nmigen btw, it has been far more pleasant so far than trying to understand how to verilog
<whitequark> :)
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