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[nmigen] anuejn commented on issue #317: Stream Abstraction for nmigen.lib - https://git.io/JtEiE
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[nmigen] anuejn edited a comment on issue #317: Stream Abstraction for nmigen.lib - https://git.io/JtEiE
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[nmigen] whitequark commented on pull request #563: Unify Xilinx platforms into a single class, support more devices - https://git.io/JtEPP
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[nmigen] whitequark commented on pull request #575: Lattice: Add support for MachXO2/XO3L internal oscillator - https://git.io/JtEXe
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[nmigen] anuejn edited a comment on issue #317: Stream Abstraction for nmigen.lib - https://git.io/JtEiE
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<Chips4Makers>
@lkcl @vup Seems we won't need Verilog file anymore for defining blackboxes; nice.
<Chips4Makers>
(Chips4Makers == Staf Verhaegen for those who don't know)
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<lkcl>
agg, vup : yes, nmigen Module rather than nmigen-Instance or verilog-Instance.
* lkcl
waves to Chips4Makers
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<Chips4Makers>
@lkcl wink
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<anuejn>
does anyone know a good intro to FPGAs in general
<anuejn>
preferably not specific to a HDL or with nMigen as the HDL of example
<anuejn>
I am looking for something that basically explains the things that one needs to know before reading the nMigen documentation
<anuejn>
(my usecase is basically that I want to reference it in the beginning of a projects documentation so that after reading that intro and the nmigen docs a person knowing python can somehow understand whats going on)
<awygle>
sadly, not really. if you come across something i'd be interested in hearing about it
<anuejn>
is that something that is generally in scope for the nMigen documentation or not really?
<d1b2>
<TiltMeSenpai> are you asking about the physical functionality of an FPGA or its programming model
<anuejn>
its programming model
<d1b2>
<TiltMeSenpai> although I guess it's a chicken and egg problem there, it's hard to talk about a programming model without a programming language
<d1b2>
<TiltMeSenpai> and the physical functionality of an fpga is just confusing until you have a solid grasp on the programming model imo
<whitequark>
it's also somewhat confusing after
<d1b2>
<TiltMeSenpai> it's just confusing in general
<whitequark>
indeed
<d1b2>
<TiltMeSenpai> fpga's (and most modern electronics) are all magic, who knows how or if they work
<d1b2>
<TiltMeSenpai> I think nmigen and/or visual HDL's may be a better place to begin thinking about the programming models of fpga's though, since they're all data structures that natively express (to some degree) parallelism and layout
<whitequark>
i've reverse-engineered an ancient CPLD (ATF15xx) and it's... i don't even know
<whitequark>
i feel like it was made using a biosimilar design process, if you know what i mean
<sorear>
the exciting question for me is "what is the Kolmogorov complexity of the routing database
<anuejn>
ah now I see the TODO at the top of the intro.rst document, so it seems to be in scope :)
<anuejn>
nice :)
<anuejn>
is that something where helping out would be good or better to wait?
<whitequark>
i already struggle to keep up with PRs at the moment, so...
<anuejn>
ok, I understand
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<Sarayan>
sorear: It's regular except where it isn't, if you get my drift
<Sarayan>
anuejn: 99% of a fpga is an alternance of lookup-table-based n:1 combinatorials followed by a flip-flop
<Sarayan>
and you really really really don't want any loops in the combinatorials, you want something beautifully structured separated by ffs
<Sarayan>
and then you can add logic blocks that give you specialized functions replacing the combinatorials, things like memories, or multipliers
<Sarayan>
even these really, really like having clocks and ffs everywhere
<Sarayan>
nmigen is nice because it is very much oriented as "on that clock, here is the combinatorial result I want you to store", e.g. it follows the fpga structure very naturally
<Sarayan>
but if your metal model is "instantaneous computation, store on a clock (possibly with a store enable)", you won't go very wrong
<Sarayan>
mental
<Sarayan>
the timing analysis will tell you how not instanteneous it really is later :-)
<d1b2>
<dub_dub_11> haha it's true, the luts are the easy part and everyone always brushes the routing under the rug
<d1b2>
<TiltMeSenpai> the routing is a problem for someone that actually understands algorithms (aka not me) 😛
<Sarayan>
Plus the routing is not something you act on