ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen · IRC meetings each Monday at 1800 UTC · next meeting TBD
<_whitenotifier-5> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/Jt6xf
<_whitenotifier-5> [YoWASP/nextpnr] whitequark 6b4fdf8 - Update dependencies.
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<_whitenotifier-5> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/Jt6p0
<_whitenotifier-5> [YoWASP/yosys] whitequark 12491e1 - Update dependencies.
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<_whitenotifier-5> [nmigen-boards] hansfbaier edited pull request #142: Add board support for Terasic de0_nano - https://git.io/Jtiqq
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<_whitenotifier-5> [nmigen-boards] hansfbaier edited pull request #142: Add board support for Terasic de0_nano - https://git.io/Jtiqq
<_whitenotifier-5> [nmigen-boards] hansfbaier edited pull request #142: Add board support for Terasic de0_nano - https://git.io/Jtiqq
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<d1b2> <286Tech> Hey can I access the contents of a Memory combinatorially? I use a Memory as the register file of my riscv processor, and I want to drive 8 leds with the contents of a specific register. Is this possible?
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<d1b2> <DX-MON> if you want the memory to be a block RAM then no, however if you don't mind it being DFF (D-Flip-Flop) resources within the FPGA, then you should be able to combinatorially assign the contents of a memory cell to a signal that goes to your 8 LED pins
<d1b2> <286Tech> Yes, but how do I actually access the contents of a specific memory cell? I only have read and write ports, but I want to access it directly.
<d1b2> <286Tech> Is it as easy as "regfile(2)" or something?
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<anuejn> you can create a new read port in the "comb" domain
<anuejn> and then assign the address you want to read to the addess input of that port
<anuejn> on the data output you will get the contents of your memory cell
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<_whitenotifier-5> [nmigen-boards] martinbarez opened pull request #143: ulx3s: fix pin mapping for audio at ring 2 - https://git.io/Jtiaa
<nickoe> How does one drive some pins as differential, for a clock out?
<agg> there's a DiffPairs resource type, instead of Pins, which you can use in the platform
<agg> what that actually does is somewhat platform dependent but hopefully just using DiffPairs in the platform will cause the correct platform-specific code to be generated
<nickoe> I am on migen, right now though.
<nickoe> but I see it also has a diffpairs thing
<nickoe> BUt I don't see that used in any board examples in litex.
<agg> I don't know about differential outputs in litex, sorry
<nickoe> Hmm, that do seem to be a nmigen only thing.
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<d1b2> <286Tech> Here's a silly demo of my riscv core acting as a counter: https://twitter.com/BitlogIT/status/1360665369929777159
<d1b2> <286Tech> I've implemented more instructions of course but this is the easiest to show visually 😄
<nickoe> I wonder how to best generate a clock that has 180 phase of another one
<d1b2> <emeb> inverter?
<nickoe> should I do it as a comb or sync?
<d1b2> <emeb> depends on your design & requirements. If you have a faster clock available and you need tight tolerance then doing it sync and re-registering the original clock will ensure they're exactly 180.
<mwk> nickoe: that very much depends what you need it for
<mwk> if you're clocking some logic on negative edge, just use neg-edge clock domain instead
<nickoe> I am trying to generate a differential clock signal to a DAC, I can't use the diff primitive thing because of the voltage levels requried for the other signals on that bank. So I am just hacking in a "differential" signal. I guess just a simple invert in between should be good.
<nickoe> But using an analog discovery 2... it seems as if the one "scope" input does not really work. mmm
<d1b2> <emeb> should work - slight phase error due to the delay thru the inverter just shifts the clock phase that the destination will see.
<d1b2> <emeb> (could change your setup/hold timing a bit)
<hell__> now I wonder, how are differential clock outputs implemented so that the signals don't get out-of-phase?
<nickoe> hell__: I gues sit is a current driver
<d1b2> <emeb> differential drivers usually have some sort of dual-transistor structure that generates both phases with tight timing relations
<nickoe> or something
<d1b2> <emeb> think a diff-amp. so you come in with one signal and both the + and - phases are generated from that with the same prop delay.
<d1b2> <emeb> then at the receive side another diff-amp is used to recover the single-end signal by essentially comparing the + and - phases and toggling at the crossing.
<hell__> I've played with a DDR3 memory controller, IIRC you can adjust both edges of some signals independently
<hell__> (on that particular memory controller, that is)
<nickoe> hell__: did you know that there is a train stop in hell?
<hell__> I guess there are no return tickets, the trains would melt once they reach that train stop
<nickoe> ok, at least it look ok https://i.snipboard.io/P9R1db.jpg
<hell__> ah
<agg> You could use the io cell registers to ensure the output signals have no phase error
<agg> Use ddr registers to set both edges if needed
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<_whitenotifier-5> [nmigen] hellow554 synchronize pull request #595: raise error on space in fsm name - https://git.io/JtK73
<_whitenotifier-5> [nmigen] codecov[bot] edited a comment on pull request #595: raise error on space in fsm name - https://git.io/JtK7B
<_whitenotifier-5> [nmigen] hellow554 synchronize pull request #595: raise error on space in fsm name - https://git.io/JtK73
<_whitenotifier-5> [nmigen] codecov[bot] edited a comment on pull request #595: raise error on space in fsm name - https://git.io/JtK7B
<_whitenotifier-5> [nmigen] hellow554 commented on pull request #595: raise error on space in fsm name - https://git.io/Jti9C
<_whitenotifier-5> [nmigen] codecov[bot] edited a comment on pull request #595: raise error on space in fsm name - https://git.io/JtK7B
<_whitenotifier-5> [nmigen] codecov[bot] edited a comment on pull request #595: raise error on space in fsm name - https://git.io/JtK7B
<_whitenotifier-5> [nmigen] codecov[bot] edited a comment on pull request #595: raise error on space in fsm name - https://git.io/JtK7B
<_whitenotifier-5> [nmigen] codecov[bot] edited a comment on pull request #595: raise error on space in fsm name - https://git.io/JtK7B
<_whitenotifier-5> [nmigen] codecov[bot] edited a comment on pull request #595: raise error on space in fsm name - https://git.io/JtK7B
<_whitenotifier-5> [nmigen] codecov[bot] edited a comment on pull request #595: raise error on space in fsm name - https://git.io/JtK7B
<_whitenotifier-5> [nmigen] codecov[bot] edited a comment on pull request #595: raise error on space in fsm name - https://git.io/JtK7B
<_whitenotifier-5> [nmigen] codecov[bot] edited a comment on pull request #595: raise error on space in fsm name - https://git.io/JtK7B