12:47 <d1b2> <dub_dub_11> is there a way I can encourage nmigen generated code to use the signed keyword rather than having signed() casts? am trying to infer DSP in ISE

15:11 <d1b2> <dub_dub_11> ah

15:11 <d1b2> <dub_dub_11> it seems like the issue is not having the inference template of verilog always @(posedge clk) begin if (fsm_state==2'h1) accumulator <= 0; else accumulator <= accumulator + (multiplicand1*multiplicand2) ; end

15:12 <d1b2> <dub_dub_11> is there any workaround generating that or would it need to be an instance?

15:14 <d1b2> <dub_dub_11> I think an instance seems reasonable here

16:36 <modwizcode> dub_dub_11: I'm fairly certain you can express the same logic in nmigen and I would be surprised if the output diverges from the form you suggested. But (not speaking from experience) I would be reluctant to assume inference on generated code, so I'd probably keep it in verilog and use Instance to ensure I get the behavior I expect.

16:37 <d1b2> <dub_dub_11> yeah i think the issue is probably the intermediate signals and all the seperate always blocks nmigen generates

16:37 <modwizcode> I'm sure there is/will be a cleaner solution but I don't know of one for DSP

16:38 <modwizcode> Yeah I would work about potential indirection through other signals, yosys seems to enjoy doing that