#nmigen on 2021-01-20 — irc logs at freenode.irclog.whitequark.org

2020-12-07 01:53 ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen · IRC meetings each Monday at 1800 UTC · next meeting TBD

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03:52 <awygle> hm. should the signal that resets a clock divider be the ResetSignal of the input domain, the output domain, both, or neither?

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06:35 <_whitenotifier> [nmigen-boards] shenki synchronize pull request #137: Add iCE40-feather - https://git.io/JttlD

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07:17 <_whitenotifier> [nmigen] tcal-x opened issue #580: Signed comparison -- difference between sim and Verilog generation - https://git.io/Jtq66

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08:55 <_whitenotifier> [nmigen] whitequark commented on issue #580: Signed comparison -- difference between sim and Verilog generation - https://git.io/Jtq9R

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09:03 <whitequark> awygle: for the PLLs so far i used the input domain reset

09:03 <whitequark> the output domain reset could be driven by the divider itself though

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20:11 <marble> is there any plan to integrate nmigen into icestudio?

20:12 <marble> would be nice to switch from verilog :D

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21:08 <whitequark> i think someone asked me about it

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