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<d1b2>
<dub_dub_11> So I was playing around with clock constraints on a design, looking at possible ways to speed it up, and noticed that (at least on the V5 I was using) the bram has output registers on the primitive itself, but there is a catch which is that it says in the ug you can't use them when inferring Bram, only when instantiating
<d1b2>
<dub_dub_11> I was wondering, if I made an instantiation template that was suitably parameterised, would it be useful to add as a feature? For example, to have a Memory() object with a "pipelined" parameter which got the template from the platform
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<mogery>
this is epic
<mogery>
whoops wrong channel sry
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<Sarayan>
modwizcode: It's kinda but not entirely working, but I'm not sure where the problem is, it may be the code on my side
<Sarayan>
AS never does to zero, which is not normal
<Sarayan>
but the microcode addresses are correct
<Sarayan>
feels like something may have gone wrong in sv2v
<Sarayan>
there's something weird though, p_Clks.get() is always zero, which is not normal (and what works shows it's not actually staying at zero)
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<modwizcode>
Sarayan: That's... interesting but might align well with something I noticed earlier which is that after flattening and running proc that some of the signals just seemed to be... going nowhere?
<modwizcode>
Did you use the most recent update to my PR though? I had to make some corrections after spending awhile playing with your unused variable discovery
<Sarayan>
Nope, I'm not up-t-date
<Sarayan>
Didn't realize you had updated
<modwizcode>
It was a small change that took all day yesterday to track down
<modwizcode>
I still think maybe the input source has issues. To my glance the output of the sv2v translator didn't seem obviously flawed but the output after running the initial yosys passes that cxxrtl runs interanlly had weird signals that were used but muxed on things that are never assigned.
<modwizcode>
OH! Important
<modwizcode>
Sarayan: I updated both PRs, I realized my changes to the clock logic might fail in certain circumstances so you need to pull in both changes
<Sarayan>
oh
<Sarayan>
Yeah, I don't 100% trust sv2v, I'm actually trying to add the mising sv features needed to load the original design
<modwizcode>
yeah that'd probably be good
<modwizcode>
Honestly my take on SystemVerilog has been to use VHDL instead or just write it in something like nMigen where I don't have to worry about stuff like that
<Sarayan>
I dudn;t write fx68k :-)
<modwizcode>
I figued (I'm pretty sure I've heard the name before) someone just needs to port it off of system verilog :op
<Sarayan>
huhu
<Sarayan>
I plan to do that eventually, but not right now
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<modwizcode>
Sarayan: Did you end up trying the patch?
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<Sarayan>
Yeah, changes nothing
<Sarayan>
wait, I forgot to change the first one too