ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen · IRC meetings each Monday at 1800 UTC · next meeting TBD
lf_ has quit [Ping timeout: 240 seconds]
lf has joined #nmigen
emeb has quit [Quit: Leaving.]
sakirious has joined #nmigen
_whitelogger has joined #nmigen
cr1901_modern has quit [Ping timeout: 256 seconds]
<d1b2> <dub_dub_11> So I was playing around with clock constraints on a design, looking at possible ways to speed it up, and noticed that (at least on the V5 I was using) the bram has output registers on the primitive itself, but there is a catch which is that it says in the ug you can't use them when inferring Bram, only when instantiating
<d1b2> <dub_dub_11> I was wondering, if I made an instantiation template that was suitably parameterised, would it be useful to add as a feature? For example, to have a Memory() object with a "pipelined" parameter which got the template from the platform
cr1901_modern1 has quit [Quit: Leaving.]
cr1901_modern has joined #nmigen
electronic_eel has quit [Ping timeout: 246 seconds]
electronic_eel has joined #nmigen
modwizcode has quit [Quit: Later]
Degi_ has joined #nmigen
PyroPeter_ has joined #nmigen
Degi has quit [Ping timeout: 246 seconds]
Degi_ is now known as Degi
PyroPeter_ is now known as PyroPeter
PyroPeter has quit [Ping timeout: 246 seconds]
Balda has quit [Ping timeout: 260 seconds]
Balda has joined #nmigen
cr1901_modern1 has joined #nmigen
cr1901_modern has quit [Ping timeout: 256 seconds]
emeb_mac has quit [Quit: Leaving.]
bvernoux has joined #nmigen
lambda_ is now known as lambda
futarisIRCcloud has quit [Quit: Connection closed for inactivity]
mogery has joined #nmigen
<mogery> this is epic
<mogery> whoops wrong channel sry
asu_ is now known as asu
boogieing has joined #nmigen
FFY00 has quit [Remote host closed the connection]
FFY00 has joined #nmigen
FFY00 has quit [Remote host closed the connection]
FFY00 has joined #nmigen
FFY00 has quit [Ping timeout: 260 seconds]
FFY00 has joined #nmigen
<Sarayan> modwizcode: It's kinda but not entirely working, but I'm not sure where the problem is, it may be the code on my side
<Sarayan> AS never does to zero, which is not normal
<Sarayan> but the microcode addresses are correct
<Sarayan> feels like something may have gone wrong in sv2v
<Sarayan> there's something weird though, p_Clks.get() is always zero, which is not normal (and what works shows it's not actually staying at zero)
Bertl_oO is now known as Bertl
cr1901_modern1 has quit [Quit: Leaving.]
cr1901_modern has joined #nmigen
chipmuenk has joined #nmigen
emeb has joined #nmigen
jeanthom has joined #nmigen
jeanthom has quit [Ping timeout: 256 seconds]
modwizcode has joined #nmigen
<modwizcode> Sarayan: That's... interesting but might align well with something I noticed earlier which is that after flattening and running proc that some of the signals just seemed to be... going nowhere?
<modwizcode> Did you use the most recent update to my PR though? I had to make some corrections after spending awhile playing with your unused variable discovery
<Sarayan> Nope, I'm not up-t-date
<Sarayan> Didn't realize you had updated
<modwizcode> It was a small change that took all day yesterday to track down
<modwizcode> I still think maybe the input source has issues. To my glance the output of the sv2v translator didn't seem obviously flawed but the output after running the initial yosys passes that cxxrtl runs interanlly had weird signals that were used but muxed on things that are never assigned.
<modwizcode> OH! Important
<modwizcode> Sarayan: I updated both PRs, I realized my changes to the clock logic might fail in certain circumstances so you need to pull in both changes
<Sarayan> oh
<Sarayan> Yeah, I don't 100% trust sv2v, I'm actually trying to add the mising sv features needed to load the original design
<modwizcode> yeah that'd probably be good
<modwizcode> Honestly my take on SystemVerilog has been to use VHDL instead or just write it in something like nMigen where I don't have to worry about stuff like that
<Sarayan> I dudn;t write fx68k :-)
<modwizcode> I figued (I'm pretty sure I've heard the name before) someone just needs to port it off of system verilog :op
<Sarayan> huhu
<Sarayan> I plan to do that eventually, but not right now
Bertl is now known as Bertl_oO
<modwizcode> Sarayan: Did you end up trying the patch?
emeb_mac has joined #nmigen
modwizcode_ has joined #nmigen
emeb_mac has quit [Ping timeout: 256 seconds]
Lofty has quit [Ping timeout: 256 seconds]
ZirconiumX has joined #nmigen
modwizcode has quit [Ping timeout: 256 seconds]
modwizcode_ is now known as modwizcode
emeb_mac has joined #nmigen
bvernoux has quit [Quit: Leaving]
moony is now known as zoomy
zoomy is now known as noomy
chipmuenk has quit [Ping timeout: 264 seconds]
jeanthom has joined #nmigen
modwizcode has quit [Quit: Later]
mogery has quit [Read error: Connection reset by peer]
ZirconiumX is now known as Lofty
danfoster has quit [Read error: Connection reset by peer]
<Sarayan> Yeah, changes nothing
<Sarayan> wait, I forgot to change the first one too
<Sarayan> I'll try tomorrow
emeb has quit [Quit: Leaving.]