<lkcl>
whitequark: star. i'll make a note of those. is there any "major showstopper bugs" which would prevent saying to NLnet "cxxrtl the basics is 100% done"?
<Sarayan>
any recommendations on how a simulation of a Instance should be done to integrate with nmigen and cxxrtl?
<Sarayan>
done as in implemented
<lsneff>
not yet, it seems
<Sarayan>
it's a very hard question, in fact
<lkcl>
daveshah i *think* you mentioned very early on that you had managed, at the yosys level, to do a mixed ilang, verilog and vhdl cxx simulation?
<daveshah>
No, that was only verilog and vhdl - I haven't tried with nMigen
<lkcl>
ahh ok. well, it would be ilang. did you convert from verilog and vhdl into ilang to do that mixed test?
<lkcl>
regardless, it's a good sign
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<daveshah>
no, I just used ghdl and read_verilog in the yosys script
<agg>
i feel like this has been discussed before but couldn't find it, is there any way to force a fifo to use a bram? afaict you can't get at the storage in the fifo as it only exists inside elaborate, so you can't add attributes to it
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