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<
chewitt >
bbrezillon can you push a branch with all the current drm/panfrost patches
05:16
<
chewitt >
looks like I have some older iterations
05:16
<
chewitt >
and I can't see anything in your github/gitlab repo(s) that matches what's on the list
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<
archetech >
chewitt: i got 5.8.8 patched running plasma on X fast
05:56
<
archetech >
wayland could use those patches I bet
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<
chewitt >
was the previous fixup! in the branch just the diff between v3 and v5 on the list?
07:21
<
chewitt >
and drop the debug bits?
07:21
<
bbrezillon >
macc24: I did start working on g72 (duet), but then swithched to g52. I'll try to get back to it next week and see if I can fix the regressions
07:22
<
bbrezillon >
chewitt: I guess so, I don't remember tbh
07:23
<
bbrezillon >
and the debug bits were just here to help me debug some of these hangs
07:23
<
chewitt >
top commit is v4 and list has v5
07:26
<
bbrezillon >
here is a version with v5 based on rc3
07:26
<
bbrezillon >
but that shouldn't change much
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<
chewitt >
bbrezillon thanks
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<
dschuermann >
I would like to merge it
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<
macc24 >
dschuermann: how to test it?
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<
macc24 >
as in what should it change?
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<
dschuermann >
something that uses the vectorizer :)
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<
dschuermann >
it might or might not change the result :P
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<
dschuermann >
(correctness should be fine, but it might create better or worse vectorizations, I mean)
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13:25
<
alyssa >
Purge 52 deleted messages? ([yes]/no):
13:25
<
alyssa >
this is my life now
13:26
<
alyssa >
dschuermann: sorry for forgetting about this, let's see
13:28
<
dschuermann >
no worries :)
13:35
<
alyssa >
Build is broken, uh oh
13:37
<
robmur01 >
pff, who has time to delete email? Current unread count here: 7036/19975 :P
13:37
<
robmur01 >
(and even that's only because O365 squirrels away everything over 2 years old...)
13:37
<
alyssa >
robmur01: I deleted 7k mails in the span of like 20 minutes this week :)
13:39
<
alyssa >
dschuermann: Did you change the should_vectorize prototype?
13:39
<
robmur01 >
...whereas I just ignored 'em and got to spend that 20 minutes being a dick on IRC instead :D
13:39
<
alyssa >
robmur01: >:
13:39
<
dschuermann >
alyssa: I changed the signature, yes. I didn't see why we'd need two instructions for that check
13:40
<
alyssa >
which commit?
13:40
<
alyssa >
I feel like I'm missing something
13:40
<
dschuermann >
because the instructions are the same anyway :)
13:41
<
alyssa >
Yeah uh that breaks nir_to_tgsi
13:41
<
alyssa >
which I guess is newer than since you last rebased so
13:43
<
dschuermann >
ok, should I rebase?
13:43
<
alyssa >
yeah, and figure out what ntt wants
13:47
<
alyssa >
dschuermann: very minor hurt for shader-db, very minor reduction in compile-time on midgard
13:50
<
dschuermann >
interesting... I assume it's the first commit that introduces the regression?
13:50
<
alyssa >
Didn't check that yet
13:51
<
alyssa >
Only 3 affected shaders in my whole shader-db
13:51
<
dschuermann >
alyssa: in the range of acceptable or should I try to figure a different solution?
13:51
<
alyssa >
Acceptable, I think
13:51
<
dschuermann >
okay, thx :)
13:51
<
alyssa >
most of the hurt is from just 1, a fragment shader that wasn't spilling before and now spills a single value (but fills 8 because our spill heuristic sux)
13:52
* dschuermann
has no idea what fills are...
13:52
<
alyssa >
spill = store to scratch, fill = load from scratch?
13:52
<
alyssa >
At least I think that's how mesa people use it, I just matched everyone else's shader-db
13:52
<
dschuermann >
ah, I always called them spill stores/reloads :)
13:53
<
alyssa >
yeah but rhyming
13:53
<
dschuermann >
true, I should update my vocabulary
13:56
<
alyssa >
dschuermann: oo, something's screwed up
13:57
<
alyssa >
if I pick just the first commit, hash_instr crashes "bad instr type"
14:03
<
alyssa >
dschuermann: ^ squash that into the first commit
14:04
<
dschuermann >
I guess that happened when re-ordering my commits. as I cannot test with ACO without the later commits :)
14:05
<
alyssa >
why's that?
14:07
<
dschuermann >
last commit: vec2 16 ssa_3 = iadd ssa_1.xz, ssa_2.xz just breaks our backend
14:07
<
dschuermann >
we can only extract scalar swizzles
14:12
<
alyssa >
dschuermann: the hurt seems to be from "rehash users of.."
14:15
<
dschuermann >
ok, that is odd. it should just avoid the need to loop the vectorizer
14:15
<
alyssa >
if I drop that commit, I get no changes for the serious afaict
14:16
<
dschuermann >
maybe if you put the vectorizer after your main optimization loop?
14:17
<
alyssa >
Currently we're vectorizing in the main loop, is that wrong?
14:19
<
alyssa >
Putting it after changes a ton of shaderdb results inconclusively
14:24
<
dschuermann >
well, it should be possible now to vectorize in a single pass
14:25
<
dschuermann >
so, not saying wrong, just different :D
14:44
<
chewitt >
currently 43,258 emails in my inbox, the oldest is from 2001 when I first registered a domain
14:45
<
chewitt >
something to clean up when I retire in 20+ years time
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<
dschuermann >
alyssa: how did you change the ntt_should_vectorize_instr? just num_components > 1? seems fragile now :/
17:00
<
dschuermann >
although.... it only adds instructions to the set if they pass the filter
17:02
<
alyssa >
I didn't, i just commented out the vectorize call :p
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17:41
<
alyssa >
so thanks to some discussion with dschuermann, it should be possible to cut the memory footprint of liveness analysis on Bifrost by a factor of 16x :)
17:42
<
dschuermann >
welcome :)
17:43
<
alyssa >
Ironically that means wading through midgard patches first... ugh
17:44
<
alyssa >
it's not that i don't like working on the Midgard compiler
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<
alyssa >
it's just that it's not the bifrost compiler.. :p
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19:31
<
macc24 >
bbrezillon: g72 panfrost when
19:32
<
alyssa >
bbrezillon: yeah, inconsistent swizzle handling is one of Bifrost's "special" features
19:32
<
alyssa >
and is the main reason 16-bit is disabled in master right now
19:33
<
alyssa >
so won't merge that patch since it's just the tip of the iceberg and we'll need a more coherent strategy to deal with it
19:33
<
alyssa >
There are a few approaches but I'm not a huge fan of any of them, scheduler seemed high priority anyway
19:34
<
bbrezillon >
sure, I'll just disable fp16 for now
19:36
<
alyssa >
but while we're on the "alyssa's brain hurts too much to finish this piece of the scheduler design" procrasination friday, I'll do some research on bifrost swizzles for you :)
19:36
<
alyssa >
I mean. for me, ultimately, but shh
20:14
<
alyssa >
Oh boy this is even more irregular than I thought
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<
alyssa >
As in it might be faster to classify everything by hand
20:15
<
alyssa >
Since... widens
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<
alyssa >
^ Classification of all the different kinds of swizzles in the ISA... it's awfully, uh, "special"
20:51
<
alyssa >
Thinking about it, probably the best way to handle is to fix the IR so searching for parent nodes is O(1) like NIR instead of O(N), and then autogenerating optimization passes for instruction selection
20:51
<
alyssa >
The alternative is to try to do everything in NIR which works for regular architectures but seems risky given how many gotchas there are for Bifrost
20:53
<
alyssa >
(There are the same issues for clamps, abs/neg, and probably some others I'm forgetting about)
21:38
<
alyssa >
Oh, gosh, the slot stuff breaks its own invariant. Great.
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<
macc24 >
hey icecream95, what's up with s3tc patch
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