azonenberg changed the topic of #scopehal to: libscopehal, libscopeprotocols, and glscopeclient development and testing |,, | Logs:
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<_whitenotifier-b> [starshipraider] azonenberg pushed 1 commit to master [+0/-0/±5]
<_whitenotifier-b> [starshipraider] azonenberg f23ebcf - Routing of LVDS data lines for pods 9-7
<azonenberg> Routed the 40GbE diffpairs plus three of the pods. The rightmost two are going to take a more awkward path layer-hopping a bit
<monochroma> :D
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<azonenberg> one challenge i'm facing is that the diffpair design rules i use for internal layers don't fit between 1mm pitch vias
<azonenberg> So i'm likely going to have to push them too close, reducing the impedance below 100 ohms differential, during the fan-out and then jump up to the correct spacing once free of the grid
<azonenberg> an outer layer pair can fit between vias/balls no problem
<azonenberg> Also i'm length matching bits within a pod tightly to minimize skew within a group of related signals, but not attempting to match too tightly from pod to pod
<azonenberg> I'll be using the IDELAYE2 for delay tuning from pod to pod
<azonenberg> in an effort to get +/- 1 bit of skew across the whole instrment
<azonenberg> then i still have to do the muxing for the high-speed inputs, the Vref/Vtt supplies, and a bunch of random support stuff like the fpga boot flash
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<_whitenotifier-b> [scopehal] azonenberg pushed 1 commit to master [+0/-0/±1]
<_whitenotifier-b> [scopehal] azonenberg 63b6d5f - RigolOscilloscope: fixed defaulting to MSO5 protocol when we should have used DS
<_whitenotifier-b> [scopehal-cmake] azonenberg pushed 1 commit to master [+0/-0/±1]
<_whitenotifier-b> [scopehal-cmake] azonenberg 21bc6cd - Updated submodules
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<_whitenotifier-b> [scopehal-apps] azonenberg commented on pull request #136: Add force trigger button to UI -
<_whitenotifier-b> [scopehal-apps] azonenberg pushed 1 commit to master [+0/-0/±1]
<_whitenotifier-b> [scopehal-apps] azonenberg 66eda6f - InstrumentConnectionDialog: assign default nickname if user doesn't pick one. Fixes #134.
<_whitenotifier-b> [scopehal-apps] azonenberg closed issue #134: Hang if I don't give oscilloscope a nickname -
<_whitenotifier-b> [scopehal-cmake] azonenberg pushed 1 commit to master [+0/-0/±1]
<_whitenotifier-b> [scopehal-cmake] azonenberg 0cffec9 - Updated submodules with bug fixes
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<azonenberg> hmmm seems like my screen recorder derped and lost some footage of the DDR3 bus layout. that's annoying
<_whitenotifier-b> [starshipraider] azonenberg pushed 1 commit to master [+0/-0/±2]
<_whitenotifier-b> [starshipraider] azonenberg b60ebea - Initial routing of DDR3 byte groups 0-3. Not optimized or length matched yet.
<azonenberg> lain, monochroma:
<lain> :D
<azonenberg> 690 unrouted now
<azonenberg> The RGMII bus will be annoying, i need to get a dozen or so single ended lines from the southwest corner of the FPGA out to the Ethernet PHY area in the northeast corner
<azonenberg> there's no good path that doesn't run under a huge number of other stuff :p
<azonenberg> lain: the fun will be length matching this all, accounting for package delays etc
<lain> yeah that'll be... fuuuuuun
<azonenberg> They want me to length match each byte group to better than 5ps vs the associated DQS
<azonenberg> Meanwhile package skew can be ~150ps
<azonenberg> although i imaigne within a group it's a lot less, but still
<azonenberg> also it warns about CK/CK# must arrive after DQ/DQS to each memory component
<azonenberg> and that i need to account for delay on the DIMM when doing this?
<azonenberg> is there a jedec spec for skew on a sodimm?
<azonenberg> I mean i still have a lot more rough layout to do before i can do the fine tuning, but still
<lain> I was pretty sure sodimm skew is effectively 0
<lain> but I might be wrong
<lain> well, what ddr is this? 3?
<azonenberg> 3
<azonenberg> I thought it was fly by routing
<azonenberg> so you have huge variations from one side of the dimm to the other?
<lain> DQ is point to point, address/control is fly by
<azonenberg> Yes
<azonenberg> But they say CK/CK# must arrive after DQ/DQS
<azonenberg> What's the propagation delay for CK vs DQS on the module?
<lain> hm
<lain> not sure
<lain> it might be in the sodimm spec??
<azonenberg> Can i safely assume every clock-to-chip path is longer than every dqs-to-chip path?
<lain> ok yeah it's specified in the sodimm jedec pdf
<lain> 4.20.18
<lain> section "Clock Control and Address/Command Cgroups"
<lain> Groups*
<azonenberg> you had that handy>?
<lain> yeah
<azonenberg> i just finished download ing it
<lain> you don't? ;)
<azonenberg> No
<azonenberg> well i do now :p
<lain> although
<lain> these numbers are length matching and not specified by delay, what the heck
<lain> I mean they do specify that they compensate for velocity differences, but...
<azonenberg> Sodimms have a temp sensor?
<lain> some do
<azonenberg> what i2c address?
<azonenberg> this might be a problem, i might have to reassign some addresses :p
<lain> lol
<lain> uhhh I forget what jedec doc governs SPD addresses
<lain> oh it's an annex to the DDR3 stuff
<lain> I don't think I have it handy, just the ddr4 one
<azonenberg> So "CTRL to CLK matching"
<azonenberg> no wait
<azonenberg> what about byte group to CK?
<azonenberg> i don't see this specified
<lain> >The length of the individual byte lanes may vary substantially across the module, with the controller providing timing realignment circuitry.
<lain> page 31, as of my copy which is release 24, revision 2.8
<Degi> The controller on the module?
<lain> I'm beginning to understand why some things only work with some sticks
<azonenberg> lol
<lain> Degi: the modules don't have controllers, they're referring to the controller in the host
<Degi> Oh, that square in the middle that there sometimes is isnt a controller?
<lain> Degi: correct
<azonenberg> On RDIMMs? that's just a buffer on the address/control iirc
<Degi> Oh
<lain> yep, it's a buffer for registered dimms
<azonenberg> lain: So looking at "raw card F" for example i see clock routes ranging from 28 to 195 mm
<azonenberg> And 24 to 30 for DQ/DQS
<azonenberg> So basically worst case the dimm clock is a tiny bit shorter than byte groups
<azonenberg> but it's generally longer
<lain> Degi: if you want more info =>
<azonenberg> If i add a relatively small amount of skew on the PCB i should be OK
<azonenberg> you agree with that?
<lain> azonenberg: agree
<azonenberg> the MIG docs say that the allowed skew is 0 to 1600 ps
<Degi> Hmh I think all signals need to be within +- 45 degrees of the clock?
<azonenberg> so if i add 250ps or so of deliberate delay from clock to longest byte group, i should be OK
<azonenberg> Degi: the design rules i have say:
<azonenberg> (UG586 page 187)
<azonenberg> * Byte group to DQS: +/- 5 ps
<azonenberg> * Addr/ctrl to CLK: +/- 25 ps
<azonenberg> CLK to byte group: -0 +1600 ps
<azonenberg> They also allow you to steal some extra timing margin by using faster RAM. So if I load DDR3 2133 on a -2 speed kintex7 and run the interface at 1600 MT/s, I can get +/- 62ps from DQ to DQS
<azonenberg> But if i loaded DDR3 1600 i'd only have +/- 31 ps
<azonenberg> and if i used a -1 speed I'd be down to the +/- 5ps from the original guidelines
<azonenberg> equally, addr/control to clock skew can go u pto +/- 124ps assumin gi use 2133 rated ram
<azonenberg> I'm going to try to match tighter than that to allow use of 1866 or 1600 rated ram if possible
<azonenberg> but it's nice to know i can steal more if need be
<azonenberg> Anyway i'm not length matching it yet. Just trying to get rough layout
<azonenberg> As you can see i'm a long way from done :p
<azonenberg> I started on the "easy" corner where i had two sides of the chip to fan out the bank
<lain> woo
<azonenberg> and it was oriented with the wide axis parallel to the side of the chip
<azonenberg> The middle bank is address/control and less full
<azonenberg> but the left one is a nearly full DQ bank and has a full bank of LVDS inputs to the left
<azonenberg> So that will be fun to fan out
<azonenberg> I think before i do more ram i want to finish the right side of the FPGA though. I need to do all of the muxes for the SERDES LA inputs, then place a bunch of bulk decoupling caps etc
<azonenberg> And i have all of the inputs from pods 10 and 11 that need to sneak into some already-full banks in the bottom center
<lain> this feels.. familiar
<lain> :P
<azonenberg> You were on a FGG484 though, not a 676
<azonenberg> so the "radius" of the chip is larger and the banks are deeper and skinnier
<lain> yep
<azonenberg> 484 is 3 banks wide, 676 is 4
<azonenberg> so you could fan out on 3 sides of the chip
<azonenberg> i only get the right and part of the top edge
<azonenberg> Of course i have 2 more layers, but they're just power
<azonenberg> Did you use vip on pipecleaner?
<lain> yeah
<lain> decoupling is SO ANNOYING without it omg
<azonenberg> yeah i know
<azonenberg> You should try using a kintex
<azonenberg> substrate decoupling caps <3
<azonenberg> almost no 0.47 uF caps
<lain> nice.
<azonenberg> mmm i love crosstalk
<azonenberg> will probably have to move some of these to other layers to space them out more
<lain> ugh I'm going to use 0201's for the smol capacitors on this design
<lain> without ViP it's too hard to fit them all close to the relevant power balls
<lain> 0.8mm pitch BGA
<lain> honestly even with ViP, 0402 is kinda big for 0.8mm pitch
<lain> but 0402 perfectly lines up with 1.0mm pitch BGA!
<azonenberg> yeah i love it
<azonenberg> luckily almost all big xilinx parts are 1mm
<azonenberg> aaand just confirmed MIG likes the addr/ctrl pinout
<azonenberg> So that's 2/3 of the dram banks routed now, not bad
<azonenberg> of course none of them are length matched yet, that's the hard part :p
<azonenberg> Managed to do addr/control entirely on two layers so i have plenty of room to move them to internal layers to space them out and reduce xtalk
<azonenberg> Good news is, at least the right part of this board is likely to have a fair bit of open space on the top layer
<azonenberg> So plenty of room for some fun artwork
<azonenberg> what do you think of maxwell's equations in silkscreen?
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<pepijndevos> In the original or modern formulation? ;-)
<Degi> Integral or differential?
<azonenberg> Lol i havent thought that far yet
<pepijndevos> No, the original did not use the concise nabla vector form, which is a later invention IIRC
<azonenberg> probably differential
<pepijndevos> Well, the answer to your question is obviously yes, so I moved on to Q 2, what format haha
<azonenberg> lol
<Degi> SI or Gauss units lol
<azonenberg> Also 40 ohm traces are annoying to work with
<azonenberg> they're massive
<Degi> 40?
<azonenberg> DDR3 is normally routed with 40 ohm impedance
<pepijndevos> TIL
<azonenberg> something about better rise times or something? not sure
<azonenberg> you can use 50 for lower speeds but when faster it has to be 40
<pepijndevos> And you're doing some 12 layers or something IIRC? So not like they could get more narrow by less layer separation.
<azonenberg> 8 layers
<_whitenotifier-b> [starshipraider] azonenberg pushed 2 commits to master [+0/-0/±5]
<_whitenotifier-b> [starshipraider] azonenberg 8fa68b2 - Initial routing of DDR3 address/control
<_whitenotifier-b> [starshipraider] azonenberg 60a28c9 - Fully escaped banks 12/13 of main FPGA
<azonenberg> ok yeah there is no way i can fan out the other two byte groups this way
<azonenberg> i'm gonna have to use too-high-Z traces then reduce to 40 ohm outside the ball array
<azonenberg> on internal layers 140um (40 ohm) traces can only fit one between balls, 89um (50) can fit 2
<azonenberg> i'll neck the 140 down to 100 which is probably around 45 ohms
<Degi> Awh a few mm of 20% more Z isnt gonna harm
<_whitenotifier-b> [starshipraider] azonenberg pushed 1 commit to master [+0/-0/±3]
<_whitenotifier-b> [starshipraider] azonenberg 74682bd - Routed a good chunk of the left side of the RAM
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<_whitenotifier-b> [starshipraider] azonenberg pushed 1 commit to master [+0/-0/±2]
<_whitenotifier-b> [starshipraider] azonenberg e413909 - Finished initial routing of DDR. No length matching yet.
<_whitenotifier-b> [starshipraider] azonenberg pushed 1 commit to master [+0/-0/±19]
<_whitenotifier-b> [starshipraider] azonenberg debdd6b - Routed most of pod 10/11 data interfaces, GTX_1V8 rail, Kintex JTAG
<azonenberg> not bad for a night's work
<azonenberg> About half of the big fpga is laid out at this point i think. Not tuned, but at least connected
<_whitenotifier-b> [scopehal-apps] whitequark opened issue #137: Opening ethernet-example.session livelocks (?) glscopeclient -
<_whitenotifier-b> [scopehal-apps] Th3Fanbus forked the repository -
<_whitenotifier-b> [scopehal-apps] Th3Fanbus opened pull request #138: Create -
<_whitenotifier-b> [scopehal-cmake] tdaede opened issue #21: cmake doesn't check for presence of yaml-cpp -
<_whitenotifier-b> [scopehal-cmake] tdaede opened issue #22: build instructions for ffts need to produce a shared library -
<_whitenotifier-b> [scopehal-cmake] grevaillot commented on issue #21: cmake doesn't check for presence of yaml-cpp -
<_whitenotifier-b> [scopehal-cmake] grevaillot edited a comment on issue #21: cmake doesn't check for presence of yaml-cpp -
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<Degi> Ooog coool
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<Degi> Huh, are there vias in pads
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