azonenberg changed the topic of #scopehal to: libscopehal, libscopeprotocols, and glscopeclient development and testing |,, | Logs:
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<azonenberg> lain: is the space under a sodimm socket an absolute keepout?
<azonenberg> or do you think i could fit an i2c thermal sensor there safely?
<azonenberg> it's <1mm high
<lain> azonenberg: max component height under the sodimm depends on the socket height
<lain> socket should spec centerline height of sodimm from board, and the jedec spec shows max sodimm height
<azonenberg> hmmm not seeing socket height clearly
<azonenberg> TE 2013289-1
<azonenberg> all of the drawings seem to be top down
<lain> upper right
<azonenberg> ah 3.3mm pcb top to center of sodimm?
<lain> I believe that's what that is indicating, yeah
<lain> (in case you're unfamiliar, a long-dash short-dash in CAD is canonically a centerline)
<azonenberg> Yeah i saw that
<azonenberg> i just read that drawing as only the mating process
<azonenberg> i missed the dimension
<azonenberg> So then i'm seeing what looks like 3.8mm as typical sodimm thickness. Or 1.9mm from centerline
<azonenberg> Which leaves 1.4mm from PCB to module
<azonenberg> Aaand the at30ts74 is 0.6mm high
<azonenberg> so i think i'll be ok?
<lain> yeah sounds fine to me
<azonenberg> Ok so at this point... i have one temp sensor on die in the stm32f7 at bottom left
<azonenberg> i2c temp sensor 1 is in the upper left corner of the board, just south of the 48-12V brick
<azonenberg> i2c sensor 2 is in the right of the power supply area, just below and left of the PLL and above the 1V2 DCDC
<azonenberg> i2c sensor 3 is right under the sodimm
<azonenberg> i2c sensor 4, not yet routed, is going to be in the bottom right corner near the high speed input muxes
<azonenberg> then the kintex has an on die thermal diode as well
<azonenberg> the spartan does not
<azonenberg> and the qsfp should have one readable over i2c
<azonenberg> That seem like decent coverage?
<azonenberg> hmm, ok so now i'm down to 3 unrouted nets on the ground layer
<azonenberg> 2 are test points and one is a mounting hole i'm debating whether to delete
<azonenberg> lain, monochroma: btw do you have any of your DDAs in working order right now?
<azonenberg> Any chance you could snag me some sata captures for later?
<azonenberg> and/or pcie
<azonenberg> or do you not have anything set up suitable for probing stuff that fast?
<azonenberg> i should probably make a sata test fixture at some point
<lain> hm
<lain> I might be able to whip something up this weekend
<lain> but we've got a house inspection tomorrow (well, today, the 17th)
<azonenberg> (also excited to see what you can throw together wrt 10GbE on my sfp fixture)
<azonenberg> at least right now, i do not support interleaving channels so you'll be running at only 10 Gsps
<azonenberg> but i think i can probably at least get an eye off of that?
<azonenberg> if i can get the pll to lock
<azonenberg> Which might be tricky
<azonenberg> interleaving kinda-sorta works if you configure it on the scope externally
<azonenberg> but iirc it causes hangs sometimes
<lain> ahh
<azonenberg> and i think i found a spot for the mounting hole
<_whitenotifier-b> [starshipraider] azonenberg pushed 1 commit to master [+0/-0/±19]
<_whitenotifier-b> [starshipraider] azonenberg 113c579 - Updating file: maxwell-main.kicad_pcb with current fully routed design.
<azonenberg> wooo
<azonenberg> still have to do planes, length matching, and lots of cleanup
<azonenberg> But it's netlist complete
<azonenberg> Need to do the artwork for the probe shells asap, they're coming tomorrow if shipping is still on schedule (haven't checked tracking in a bit)
<pepijndevos> wohooo
<pepijndevos> congrats
<azonenberg> also bonus points to anybody who gets the reference in the commit message
<azonenberg> (and i feel sorry for you if you've spent enough time with that software to recognize it instantly)
<pepijndevos> The "updating file" one? Seems very generic
<azonenberg> Google it (without the file name)
<pepijndevos> I'll not spoil it for anyone wanting the bonus points, but I have not had the misfortune to use this tool. My uni used the other big vendor and it's been FOSS since then.
<azonenberg> Lol
<azonenberg> yeah if you've spent enough time trying to get timing closure on their chips as i have... :p
<azonenberg> pepijndevos: i've actually been doing that for a while as a bit of an easter egg in commit logs any time i finish a design lol
<sorear> didn't realize you were to the point of modeling heat and airflow and "how many fans do I need"
<azonenberg> sorear: i used the xilinx power estimator for the fpga and datasheet estimates for power consumption on the PLL, those were the two hottest things
<azonenberg> the 4 fans should be overkill, i likely will only use the 2 on the main board, but i'm provisioning for two more off to the side if needed
<azonenberg> realistically i likely wont even run the 2 at full RPMs, the thermal calculations were quite worst-case
<pepijndevos> hah, commit message easter eggs...
<pepijndevos> I once was in a huge uni group project with a dozen people who we managed to convince to use git rather than google drive for our code
<pepijndevos> There was this one useless guy (as all group projects are required to have by law), who was given various small tasks to keep him occupied and out of everyones way
<pepijndevos> One such task was to write a bit of Python code to talk to some SPI DAC chip we attached to a pi
<pepijndevos> So for like an entire week this guy would make git commits saying just ""
<azonenberg> oh so many memories of group projects in school... i remember one where we ended up with not a single line of my teammates' code in the final project
<pepijndevos> And then everyone started doing it for other unrelated commits. And that is... how I ended up hiding references in my thesis presentation.
<azonenberg> lol
<pepijndevos> > i remember one where we ended up with not a single line of my teammates' code in the final project
<pepijndevos> thats seems normal
<pepijndevos> It was a fun time to experiment with ways to collaborate... or not
<azonenberg> So funny story
<azonenberg> I was taking a class called "advanced computer hardware design"
<pepijndevos> sounds fun
<azonenberg> Which wasn't truly advanced, i was hoping it would be about pcie fpga stuff and ddr3 layout and such
<pepijndevos> I feel that
<azonenberg> no, the first lab assignment was fixing an incompletely implemented IDE hard drive controller
<azonenberg> Running on an XC4000 FPGA on a... i forget if it was PCI or ISA... card plugged into a DEC Alpha
<azonenberg> This was in like 2011
<azonenberg> Using fpgas with 1996 date codes on them
<azonenberg> Then we built a 4-bit CPU on a... DE0 i think? in schematic capture, no HDL. Because that's totally how people do chip design nowadays
<azonenberg> anyway i was fed up with this. So for the final project i decided to do something more interesting and less stuck in the last century
<azonenberg> So i proposed a simple MIPS based SoC (this was pre riscv being mainstream) with a cpu, uart, and some caches
<azonenberg> I told them i'd do the CPU myself, as well as writing a memory mapping wrapper around the existing UART IP i had written
<azonenberg> all they had to do was build I- and D-side L1 2-way set associative caches
<azonenberg> For a half semester project
<azonenberg> (In verilog, targeting a spartan6 board i had built)
<azonenberg> well, despite my best attempts to get them to cooperate, they basically dropped off the map
<azonenberg> I built a 5 stage pipelined textbook mips1 cpu, had C compiled with GCC running on it multiplying matrixes generated by a PRNG
<azonenberg> built a simple direct mapped L1 cache as a testing mock for their cache
<azonenberg> well, a week before the assignment was due they handed me their code
<azonenberg> Which neither worked, nor conformed to my bus protocol
<azonenberg> It was beyond repair
<azonenberg> So i did the demo for the class using the direct mapped cache
<pepijndevos> lol
<pepijndevos> In my digital hardware course the project was pretty free, you just get a DE-1 SoC and a Raspberry Pi. The interesting bit is it's shared with computer science who don't learn the FPGA stuff so you have to come up with something that uses both the Pi and the FPGA.
<pepijndevos> The strange part is that for practically anything you can push to the FPGA over the provided interface board, the Pi can do it faster.
<azonenberg> lol
<azonenberg> not enough bandwidth? i mean pi's are not known for having great io options
<pepijndevos> But I was fortunate enough to have at least one competent CS guy, so it was basically him and me.
<pepijndevos> Yea, fastest you could do is use the hardware SPI of the Pi
<pepijndevos> The inputs were buffered too
<pepijndevos> Which is good, because a fair number of groups managed to destroy the clamping diodes on the FPGA
<pepijndevos> Anyway, the assistants were just like... yea, just make something that uses both ok?
<pepijndevos> So the CS guy hacked gambatte to write graphic memory to the FPGA, and I implemented the gameboy graphics on the fpga.
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<pepijndevos> Can I use the signal generator on the Rigol while using glscopeclient?
<azonenberg> pepijndevos: Define "use"
<azonenberg> having glscopeclient open will not stop you from using any front panel controls
<azonenberg> however there is no UI in glscopeclient for function generator features of scopes
<pepijndevos> oh ok, yea I was kind of thinking it takes control
<azonenberg> libscopehal does support basic function generators, and there's support for the integrated generator on LeCroy WaveSurfer 3000 series, but it's just an API right now and there's no UI to access it
<pepijndevos> Because weird things happen if you use the front panel with glscopeclient open in my very very limited experience
<azonenberg> Adding support for rigol's generator to the RigolOscilloscope class would be pretty easy
<azonenberg> Interesting
<azonenberg> The main thing that doesnt play well is if you mess with arming/disarming the trigger
<azonenberg> glscopeclient expects to manage all triggering and gets confused if you, say, disarm the trigger while it's waiting for something to happen
<pepijndevos> But maybe it's more that glscopeclient changes a lot of setting when it opens
<azonenberg> Yes
<pepijndevos> cool
<azonenberg> the big thing it does is enable all channels by default
<azonenberg> because otherwise the UI would be empty
<pepijndevos> right
<azonenberg> it shouldnt mess with that many other settings out of the box, it mostly queries the scope to figure out settings and runs with those
<pepijndevos> I'll update my graphics drivers, and see if the thing works normally again
<_whitenotifier-b> [starshipraider] azonenberg pushed 1 commit to master [+0/-0/±1]
<_whitenotifier-b> [starshipraider] azonenberg fe97b63 - Added ground planes to layers 2 and 7. Began power plane layout on layer 4.
<pepijndevos> So basically I built an IC on breadboard... and I'm thinking I want to make a video with it to show off the chip, so I want to set up OBS and glscopeclient, but yea, I need to mess with the signal generator.
<azonenberg> power layers so far btw
<noopwafel> azonenberg: \o/ on netlist complete
<azonenberg> noopwafel: yeah at least a week to full completion though
<azonenberg> lots of power layout, design review stuff
<azonenberg> then i have to respin the pod PCB with the SFF connector moved and power for the LCD added
<Degi> Oh nice :D
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<_whitenotifier-b> [starshipraider] azonenberg pushed 1 commit to master [+0/-0/±1]
<_whitenotifier-b> [starshipraider] azonenberg 5573678 - Continued power plane layout on layer 4
<azonenberg> layer 4 power plane layout proceeding nicely, probably about 3/4 done
<azonenberg> layer 5 power untouched so far
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<azonenberg> Yay the mail is being slow. Probe shells and MEAD enclosures are now ETA tuesday, not today
<azonenberg> o/ Katharina
<azonenberg> How goes it? Been up to doing any more coding yet or still pretty out of it?
<Katharina> azonenberg o/
<Katharina> every day it is better
<Katharina> been doing some python today and yesterday, and its going ok so far
<azonenberg> Yay
<Katharina> sadly, two coworkers are now also sick
<azonenberg> Think you got it from the office or what?
<azonenberg> I thought you were pretty much all remote still
<Katharina> i am pretty sure i contracted it the one day i was in the lab with the two collegues that are now also sick
<Katharina> but i cant tell you for sure
<Katharina> or, I infected them.
<azonenberg> yeah one of you probably infected the others
<azonenberg> welp, hope they recover ok
<azonenberg> Anyway i'm not touching any of the stuff you were doing in ui-dev, when you feel ready to get back to it it'll be waiting
<azonenberg> I've been mostly pushing on the hardware stuff the last few weeks anyway
<azonenberg> Did you see the flattening of scopehal-apps + scopehal-cmake a week or so ago, btw?
<azonenberg> when you get back to development scopehal-apps should be the new top level repo, scopehal-cmake is no longer in use (I kept the repo as archived for now)
<_whitenotifier-b> [starshipraider] azonenberg pushed 1 commit to master [+0/-0/±1]
<_whitenotifier-b> [starshipraider] azonenberg 5e5b113 - Began layer 5 power plane layout
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<Katharina> azonenberg: yes i did! i think its a good thing
<azonenberg> For now i'm keeping the library and apps separate
<azonenberg> that's a far more logical split
<Katharina> it definitely is
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