azonenberg changed the topic of #scopehal to: libscopehal, libscopeprotocols, and glscopeclient development and testing |,, | Logs:
<azonenberg> ooook so the v0.9 probe is assembled
<azonenberg> It's definitely the best yet, but a fairly incremental improvement on v0.9
<azonenberg> So, worst to best... the navy blue trace that's all over the place is the pico ta061 probe with the long alligator clip ground wire
<azonenberg> as you can see it's garbage beyond like 250 MHz :p
<azonenberg> Next worst is the green trace with the big peak at ~670 MHz, that's the pico ta061 with the spring ground
<azonenberg> That has -3 dB bandwidth of about 1.2 GHz
<azonenberg> the red is almost the same, it dips instead of peaking and has -3 dB bandwidth of about 1.15 GHz. That's my probe with the Z-ground
<azonenberg> With the big fat ground leaf, my probe is decently flatter and gets out to 1.4 GHz.
<azonenberg> (blue)
<azonenberg> Then the best performer by far among this group is my probe with the close ground right next to the tip. That gets out to 1.85 GHz
<azonenberg> not quite 2, but halfway decent and way better than the pico
<monochroma> oooo yeah that's pretty nice
<azonenberg> and this is with ENIG losses too
<azonenberg> i think i could probably hit 2 if i fabbed this layout on rogers with silver
<monochroma> oh ! cool!
<azonenberg> then probably in the 1.2-1.5 GHz range with the other accessories
<azonenberg> see, most probes dont tell you how bad they get when you use anything but the most optimized, short ground leads :p
<azonenberg> I intend to actually characterize typical performance in each case
<miek> heh, yeah. i bet all the normal 10x probes are specced by plugging them into a perfect socket
<azonenberg> long shot of my probe with the 3 diff ground options
<azonenberg> the leaf is, interestingly, not actually that much better than the z-ground
<azonenberg> but the close ground is much nicer. and the rolloff is far smoother
<azonenberg> this leads me to believe most of my remaining performance issues are ground inductance on the red/blue traces, which i cant do much about
<azonenberg> and enig losses on the pink trace, which i can fix by going to 4350B
<azonenberg> and yeah these arent ideal sockets
<azonenberg> these are actual tip+ground measurements touching a real PCB with a 50 ohm terminated line on it
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<azonenberg> monochroma: anyway i think these are probably good to go
<azonenberg> gonna take one last look at the design then send 'em out to multech for the production run
<azonenberg> then in a week or two order the resistors, i need to check my inventory and see how many more i need to buy (i have a fair number in stock now)
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<_whitenotifier-f> [scopehal-apps] azonenberg opened issue #126: Protocol overlay Y position is not saved in scopesession files -
<_whitenotifier-f> [scopehal-apps] azonenberg labeled issue #126: Protocol overlay Y position is not saved in scopesession files -
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<_whitenotifier-f> [scopehal-apps] azonenberg opened issue #127: Allow cursors to be synchronized between viewports -
<_whitenotifier-f> [scopehal-apps] azonenberg labeled issue #127: Allow cursors to be synchronized between viewports -
<_whitenotifier-f> [scopehal] azonenberg pushed 2 commits to master [+2/-0/±6]
<_whitenotifier-f> [scopehal] azonenberg a50b2ae - Initial implementation or IPv4Decoder. Not complete.
<_whitenotifier-f> [scopehal] azonenberg 5bf1fe1 - IPv4Decoder: finished initial implementation. Doesn't do packets yet.
<_whitenotifier-f> [scopehal-docs] azonenberg pushed 1 commit to master [+0/-0/±1]
<_whitenotifier-f> [scopehal-docs] azonenberg 4bcbe81 - Clarified some things in Ethernet section, added blank heading for IPv4 decode
<_whitenotifier-f> [starshipraider] azonenberg pushed 3 commits to master [+0/-0/±23]
<_whitenotifier-f> [starshipraider] azonenberg 1ca1bc8 - Initial placement/routing of comparators for fast input pod
<_whitenotifier-f> [starshipraider] azonenberg b75201c - Added decoupling caps to Vtt rail on U37. Initial routing of PPS and external trigger inputs.
<_whitenotifier-f> [starshipraider] azonenberg 555a219 - More tweaks to external input area
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<azonenberg> so today i did the comparator for the PPS and external trigger inputs, as well as the comparators for the fast inputs and a bunch of miscellaneous housekeeping stuff like a few more probe power switches
<azonenberg> About 2.5K unrouted still
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<Degi> Where are the 3D models for the power converters from
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<oskar> Hello!
<monochroma> hai
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<azonenberg> Degi: they're approximate DOSA brick models from other power supply vendors that make pin compatible parts, in most cases
<azonenberg> the Murata and Recom modules are actual vendor step models
<azonenberg> but the bigger ones i couldn't find any official models for so i did the best i could. Same dimensions and pinout which is really the key bit
<azonenberg> LeoBodnar: ping
<LeoBodnar> ayup
<azonenberg> LeoBodnar: do any of your GPSDO modules have PPS outputs?
<azonenberg> if not, any plans to release one that does?
<azonenberg> (also any plans to integrate GPSDO w/ PPS and NTP server functionality in a single unit?)
<LeoBodnar> large GPS clock has but it's directly off the GPS module
<azonenberg> What kind of precision does it have?
<LeoBodnar> so it has ~10ns quantisation uncertainty
<azonenberg> That's probably good enough for my purposes. I wanted to use it for timestamping trigger events in MAXWELL
<azonenberg> use NTP to get time to nearest second then PPS for the low bits
<azonenberg> there will be clock domain crossing uncertainty etc in the FPGA anyway
<LeoBodnar> I am still in the middle of the board level module design, but it's coming to the prototype level
<azonenberg> GPSDO+NTP you mean?
<azonenberg> Awesome
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<azonenberg> What form factor were you thinking?
<azonenberg> any chance of getting it rackmountable via some sort of adapter?
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<azonenberg> That PLL board we talked about a while ago is still on hold while i work on higher priority stuff, but is very much on the to-do list still
<LeoBodnar> excellent
<LeoBodnar> I am reshuffling NTP design and it will get e bigger enclosure that might be able to accommodate the GPSDO board
<azonenberg> So something that is either 1U high or at least fits on a 1U shelf would be ideal
<LeoBodnar> sure
<azonenberg> ideal would be a swappable front panel probably
<LeoBodnar> yeah this is the plan atm
<azonenberg> Perfect. so you can just drop in the standalone skinny or full 19" width panel to rack it?
<azonenberg> now i just have to think about maybe getting taller racks on my test equipment benches...
<azonenberg> Right now between DSOs, patch panels, power supplies, and DMMs i have 4U free on the right hand rack and 3U on the left
<azonenberg> If i move the PSU+DMM combo up to the top of the rack, which makes sense as i dont need to touch those super often and they don't have length-critical RF cables coming off the front like scopes etc do, i can reclaim 1U because they need 1U above/below for airflow
<azonenberg> So i could fit the PSU, DMM, and a single new 1U device at the top of the rack, then the scope and cable management bar, then i could probably remove the BNC patch panel and have 3U free at the bottom of this rack
<azonenberg> So if i had the GPSDO+NTP at the top i could put the clock distribution module at the bottom and still have 1U free for a MAXWELL system plus 1U for one of our headless scopes
<azonenberg> And at that point i'd have 3-4U available on the left hand rack, depending on how i set things up, for new instrumentation
<azonenberg> The real question is how many outputs i can fit on the back of my refclk distribution system? because i'd want to send the GPSDO output clock to a minimum of four instruments (two DSOs, MAXWELL, and a scopehal scope) and probably several more
<azonenberg> Especially once we start building signal generators and stuff
<azonenberg> i might actually want to make two of the refclk systems to get extra outputs because the pll can only do fine phase control on five or six outputs
<azonenberg> or i could try and fit two PLLs into one chassis, will have to see how the dimensions work out
<azonenberg> then just have a splitter coming off of the initial 10 MHz clock to each one
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<Degi> Can u attach 50 ohm splitters
<Degi> I mean behind a 1U you could fit a lot of SMA
<azonenberg> yes you can attach splitters but then you don't get phase control
<azonenberg> half the point of this project was to have cable deskew
<azonenberg> so every instrument sees the 10 MHz rising edge at the same time
<azonenberg> no matter how far it is from the GPSDO
<Degi> Oh well then put like 50 SMAs onto a 1U
<azonenberg> lol
<miek> just need stretchy cables
<Degi> lol
<Degi> Dynamic phase adjust
<_whitenotifier-f> [starshipraider] azonenberg pushed 1 commit to master [+0/-0/±4]
<_whitenotifier-f> [starshipraider] azonenberg 5909ad6 - Initial routing on refclk comparator
<azonenberg> So i moved the dram and roated the fpga, i think this is a better design because i don't have to dodge the ddr bus when routing the inputs anymore
<Degi> Hmh cant u change pins on the FPGA such that the routing is easy and without crossing?
<azonenberg> also swapped the high and low byte groups on the dram so now things look a lot saner there
<azonenberg> The DRAM has to be on specific banks because not all of the banks are the same in hardware
<azonenberg> and the SERDES are also on dedicated pins
<azonenberg> So that basically restricts me to one of two possible orientations. First is ram on west side, serdes in northeast corner
<azonenberg> other is ram on north side, serdes in southeast corner
<azonenberg> serdes have to be on the east side because that's where the fast inputs and the 40GbE port are
<azonenberg> i think ram at north makes more sense because it frees up the west side of the fpga for routing from the west-most probes
<Degi> I mean you could still change ordering within banks so that you can minimize trace crossings
<azonenberg> The other question is exactly where to put the FPGA. Further east means closer to the 40G port and less loss there, plus more space around the PSU area
<azonenberg> but further west makes it easier to length match the probe signals
<azonenberg> and yes the issue i was having was that ~30 LVDS pairs would have had to sneak underneath the DDR bus which was a very congested area
<azonenberg> and there wasnt much space around it
<azonenberg> anyway i want to length match the lvds as much as i can to avoid lane to lane skew
<azonenberg> i can fine tune with IDELAYs but i want to at least get in the general ballpark
<Degi> How many layers are you targeting anywys
<azonenberg> So i want to avoid having the fpga too far east of the centerline or the center/east links will need huge amounts of squiggles
<azonenberg> Eight. no way this would be doable in six
<azonenberg> too many power rails
<Degi> You can route the west side in a big loop
<Degi> THen youd need less squiggle
<azonenberg> you misunderstand, my concerns is not the west, it's the links at the south right under the fpga
<azonenberg> those need to be length matched to the super long stuff coming from the west
<Degi> Hmm cant you make them in a loop too
<Degi> Like a big S
<azonenberg> that would use a huge amount of routing area i need for other stuff
<Degi> But yeah rather avoid that
<azonenberg> you underestaimte how congested this design is going to get
<azonenberg> Good news is, i'm only sampling at about 1 Gsps and i'm willing to tolerate probably +/- 1 sample of skewe between lanes
<Degi> Or move the LAN port to the middl
<azonenberg> 800ps is a fairly easy skew target to make
<azonenberg> So i can probably add much less meanders than i would have to get all lanes to within, say, +/- 500ps of each other
<azonenberg> i can also route the longer links on... external, i think? layers which have faster propagation velocity
<azonenberg> since air dielectric
<Degi> yes
<Degi> Huhh 4L on JLC is 26 $ with ENIG and 6L is like 100
<azonenberg> yeah that is cheap fr4 :p
<azonenberg> and probably no impedance control, etc. jlc is a low end cheap fab and i'd never use them for something like this
<azonenberg> also how big a board? this is about the size of a sheet of A4 paper
<Degi> Hm yes with impedance control
<Degi> But I doubt that they explicitly test it
<azonenberg> on Rogers
<Degi> Ahh yes 100*100 mm and 5 pcs, default size
<miek> jlc's impedance control means they use an impedance calculator and adjust trace widths, btw
<Degi> yes
<miek> it's not "control"
<Degi> Wait they adjust my trace width?
<Degi> A literal A4 sheet of 1.6 mm is 86.3 $ heh
<Degi> Huh, JLC says " Pls prototype PCB first, then use the "Reorder" function for small batch production. " above 2500 pcs
<miek> hm, good point. i don't remember there being a way to tell them what traces you want controlled
<Degi> I think they just ensure that the stackup is specified
<Degi> Otherwise I guess its random
<miek> yeah
<azonenberg> miek: aaaand this is why i use "real' fabs for fast stuff
<miek> yup
<azonenberg> good luck getting this out of JLC
<miek> i like JLC and use it for a bunch, but more people need to understand what they're getting :)
<Degi> I mean yes but it also costs a few hundred lol
<Degi> Like for examp,le PCIe allows like 12 dB loss
<azonenberg> yeah one of the reasons i went with rogers here is because i had some very long diffpairs and the fpga does not have equalizers on the normal GPIOs
<Degi> At JLC 1 layer can cost more than 2 layer lol
<azonenberg> (also because 40G)
<Degi> Huh, for 22 k you can get 2000000 PCBs from JLC
<Degi> Of size 10x10 mm
<Degi> Or for 1.7 M you can get 438 million of 6x6 mm haha
<Degi> I wonder if they would actually MFG that
<Degi> You can reduce that cost to 224 k for 144 M PCBs which is like 0.2 cents per pcb haha
<Degi> Imagine building a house out of 4800 kg of PCB
<azonenberg> imagine a house that doesnt need any mains power wiring because it's all printed directly onto the fr4 panels the walls are made of? :p
<Degi> And wifi antennas lol
<Degi> And you could make the outside look pretty cool
<Degi> Hmm, structural elements made from PCB and solder them together
<Degi> Your life expectancy would decrease by like 10 years from PCB fumes
<azonenberg> lol
<bvernoux> azonenberg, the Multech certificate with chinese mixed with english ;)
<bvernoux> personally I'm not fan of such certificate as there is so much fake ....
<azonenberg> Yeah except they send you the actual test samples they did the measurements on
<azonenberg> and so far in my limited testing i haven't found any errors
<azonenberg> they do that specifically so people won't say they didn't just make up the numbers :p
<bvernoux> yes great
<bvernoux> it seems serious anyway when we see the report it is just I saw so much Chinese/English report like that and even more with COVID for masks ;)
<bvernoux> that we are a bit paranoid that it is full fake ;)
<bvernoux> more than 90% of masks produced are not compliant
<bvernoux> I know with PCB it is different ;)
<bvernoux> but some PCB manufacturer have switch to build masks to gain more money ;)
<bvernoux> and it seems to be a disaster as nothing is compliant as it is clearly not the same work ;)
<Degi> lol
<_whitenotifier-f> [starshipraider] azonenberg pushed 1 commit to master [+0/-0/±3]
<_whitenotifier-f> [starshipraider] azonenberg 142387f - Layout of PLL subsystem
<azonenberg> lain, monochroma: ^
<azonenberg> Rapidly starting to look more tractable
<azonenberg> I'm debating how to proceed next. There's a few little things like the power switching for the leftmost two probe pods etc, but for the most part the remaining work is power supply plus the three big BGAs
<azonenberg> and i haven't locked down the positions of any of them yet
<azonenberg> i've been kinda doing a fan-in style layout where i start by anchoring the I/O to the fixed locations then hook up the directly attached stuff to them
<azonenberg> then work my way inward
<Degi> Heh yes
<azonenberg> But i'm starting to run out of anchored things to do
<azonenberg> i guess i could start with some of the PSU stuff
<azonenberg> but i think it might make more sense to design the PSU around the logic and not the other way around
<azonenberg> let it flow around as needed since its lots of little modules
<Degi> Hmh, the SFP directly goes to the FPGA?
<azonenberg> Yes
<azonenberg> (also it's a QSFP+, four serdes lanes)
<Degi> yes
<azonenberg> I debated putting ESD diodes on but decided there was no point
<azonenberg> you'd have to stick your hand into the socket or something to zap the contacts
<Degi> yes
<azonenberg> the module is grounded long before it mates
<Degi> Maybe with a DAC cable
<azonenberg> anyway, so yeah it's coming together nicely :)
<azonenberg> I think the next step is going to be anchoring the stm32 to its final location. It needs to be near the left side because it controls all of the power rail sequencing as well as the LCD so the majority of things it talks to are out there
<azonenberg> and then i can get all of the decoupling and support stuff out of the way once it's done
<azonenberg> Should at least declutter the ratsnest a bit
<Degi> Wow im so bad at staying focused lol
<Degi> *Actually finds the solution of the homework on page 7 of some PDF I've opened before going on adventures on wikipedia and the JLC price calc*
<Degi> Tbh DAC cable is like LCD display
<azonenberg> or atm machine? :p
<Degi> lol
<Degi> smh my head
<Degi> Hmh on the PCB report they have max and average seemingly swapped on PCB impedance
<Degi> Can they make a PCB on PTFEbasis
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