azonenberg changed the topic of #scopehal to: libscopehal, libscopeprotocols, and glscopeclient development and testing |,, | Logs:
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<_whitenotifier-3> [scopehal] azonenberg closed issue #165: Refactoring: change "protocol decoder" to "filter" in all class/function names etc -
<_whitenotifier-3> [scopehal] azonenberg closed issue #148: Attach units to protocol decoder parameters for better pretty-printing/parsing -
<_whitenotifier-3> [scopehal] azonenberg closed issue #229: Add support for filters that have multiple outputs -
<_whitenotifier-3> [scopehal] azonenberg pushed 5 commits to master [+86/-84/±98]
<_whitenotifier-3> [scopehal] azonenberg da87733 - Initial skeleton of OFDMDemodulator filter. Will be testbed for new multi-stream architecture.
<_whitenotifier-3> [scopehal] azonenberg f55570d - Renamed ProtocolDecoder to Filter. Fixes #165 (but needs to be propagated to all derived classes still). Added units to parameters. Fixes #148.
<_whitenotifier-3> [scopehal] azonenberg 845d828 - Refactoring: removed legacy toQueue argument from all scope drivers. Fixes #132.
<_whitenotifier-3> [scopehal] ... and 2 more commits.
<_whitenotifier-3> [scopehal] azonenberg closed issue #132: Remove support for non-queued acquisition mode in Oscilloscope::AcquireData() -
<azonenberg> well, that was almost a 13K line diff
<azonenberg> Lots of cleanup and closed a ton of longstanding tickets
<azonenberg> These fixes are applied to the library only, glscopeclient does *not* currently build against master libscopehal
<azonenberg> Going to bed now but will be doing the UI-side changes tomorrow
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<kbeckmann> This shows how little i know about how scopes work under the hood, but would it be possible to implement a "sampling oscilloscope" mode with BLONDEL etc? As far as I understand it, you simply sample multiple times but with an increasing phase shift? Would this make it possible to get eye diagrams etc of very high signals, say 10GHz with the 1GS/s ADC?
<kbeckmann> very high speed signals*
<tnt> you still need the analog bandwidth to do that.
<kbeckmann> right.
<tnt> but there was another board that was targetted at being a sampling scope ...
<tnt> can't remember the name.
<tnt> not sure if azonenberg has a published list of project name with short description somewhere :p
<miek> i think the hard part then becomes controlling that phase shift well enough (and trigger jitter etc.), which might not be possible if the scope wasn't designed for it
<kbeckmann> okay interesting. i'm just thinking if it would be worth making something modular so you can reuse the fpga+adc and switch out the analog frontend
<kbeckmann> yeah that makes sense..
<miek> did you see Ted Yapo's supercon talk & sampling scope project?
<kbeckmann> it sounds very familiar, i should check it out again nonetheless.
<kbeckmann> nice!
<Degi> If you do it with an ADC instead of with a comparator as azonenberg did, you need a fast S/H buffer. I found one recently which has 20 GHz BW but it costs like 1 k$ for a single chip ;(
<kbeckmann> ah yes that makes sense.. ouch, but that could still be worth it perhaps.
<monochroma> i wonder what kind of performance you could get out of a discrete design
<Degi> Hmm now I wonder. Could you use a mixer instead which has 3 ports with DC-20 GHz?
<Degi> I designed a discrete circuit once for estimating the time between two pulses (comparator output and clock signal) once, though somebody would need to build it and have the proper test equipment and its kinda dubious whether it works at all (in simulation it does, but I didn't simulate all parasitics, only very basic stuff).
<Degi> On the other hand, it would be real cheap lol.
<Degi> I mean if you have an ideal mixer which does out = in1 * in2 and you feed it a delta peak signal (for example generated by those soviet step recovery diodes on ebay), the output should be that short peak multiplied with the input signal. Integrating the output over 1 ns and having a delta pulse width of 50 ps would yield 20x attenuation but then the AFE only needs 1 GS bandwith
<azonenberg> tnt, kbeckmann: yeah, freesample is a from the ground up sampling scope designed wot work with scopehal
<azonenberg> designed to*
<azonenberg> Schematic is done, layout is around half to 3/4 done, but i want to go back and tweak a lot of stuff. I did the design before having bought Sonnet
<azonenberg> And for example i don't think the input SMA as it's currently laid out would be good anywhere near 10 GHz
<azonenberg> So i have a bunch of stuff i want to fix
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<miek> tnt: did you get the agilent driver working ok for what you wanted the other day btw?
<azonenberg> I pushed a bunch of changes to every driver last night so if you are planning to do more driver dev work you should redo your patches on top of this
<azonenberg> big changes are removal of the toQueue mode (now *all* acquisitions go into the queue, there's no way to avoid it and go direct as that mode was never used) and some glue for multi stream outputs
<tnt> miek: yes
<miek> cool :) i had done a bunch of changes for channel/trigger/etc. controls so good to know those didn't break on yours
<tnt> miek: yeah, the issue was just timeout ... the scope takes a while to load the list of installed options and this was timing out, causing all scpi query/response to be out-of-sync.
<tnt> I just disabled timeouts all together ...
<Degi> I wish I had access to a 4+ GHz scope... Really wanna try out that mixer + impulse generator S/H idea.
<Degi> I wonder how much bandwith can be increased by adding a highpass filter before ADCs
<azonenberg> Degi: if you design and build a board and provide me with testing directions, i can characterize it for you?
<Degi> Hmm maybe I could...
<Degi> I wonder if I could ask around at uni a bit whether one of the profs has one, but that's a bit impractical with the current covid situation (they have pretty strict rules)
<azonenberg> i have a bunch of FPGA boards, a 2 port VNA that can also be used as a pure sine generator from a few kHz to 6 GHz (no modulated RF generation capability at this time, although i can do fast pulses with FPGA SERDES)
<azonenberg> and a 2 and 4 GHz 40 Gsps scope
<azonenberg> so if you can design a test procedure based around that, i'll gladly run it for you
<Degi> Hm cool, do you have a high frequency mixer which can do low frequencies (few tens of MHz or lower, preferrably DC) too?
<Degi> Your SERDES can do 100 ps pulses, right?
<azonenberg> I do not have any RF mixers
<azonenberg> as far as serdes go, i can go all the way down to whatever the Fmax of a VCU118 serdes are. although i dont know if they have any brought out to SMAs
<azonenberg> I do not currently have any kintex7 devkits w/ serdes
<azonenberg> i also have an AC701 which goes up to i think 6 Gbps on the serdes
<Degi> Ah, kintex7 is the one in the LA project with 10 GS/s?
<Degi> On the other hand, I'm not sure how feasible that is. It would pretty much only replace what you currently do with a comparator, so instead of searching a 2d space it would only need to search a 1d space. Downside: I can't seem to find any fast mixers which go down to nearly DC...
<Degi> I wonder if you could split the path up to different mixers, one to handle 0-10, one for 10-20 GHz etc.
<azonenberg> That sounds like what lecroy did in the labmaster stuff
<azonenberg> it's possible but getting good performance at the band edges with ultrasharp cutoffs is really hard
<Degi> Hm yes I guessed... I wonder if you can do smooth cutoff and interpolating in gateware or so
<azonenberg> also you have to maintain phase coherence between them
<Degi> I think that should be doable
<tnt> calibration becomes quite critical when doing that.
<Degi> Yes
<Degi> And thermal effects etc
<Degi> This could make for a cheap sampling scope.
<Degi> It only works for big signals though, like 1 V amplitude would be nie
<Degi> *nice
<Degi> This is how the intermediate signal looks like...
<Degi> Actually it seems to work better with small signals, but needs a large DC bias
<Degi> And a precise on voltage for the transistor
<NeroTHz> I see RF mixer and sampling scope and VNA
<NeroTHz> what did I miss
<NeroTHz> Speaking of mixers as samplers, there is actually a bit of overlap in how they work, in some sense. If you have a ´discritizing sampler´ that has 50% dutycycle, you kinda made a mixer
<Degi> Usually samplers haver very low duty cycle
<NeroTHz> sure, but conceptually, it´s not uncommon for them to be very similar, even in design I think
<Degi> Oh cool, might actually try building this circuit with a few different transistors.
<Degi> The output you see is the output of a sample at time x, delayed by 2 ns. Basically the simulation runs 81 times and for 2 ns there is a sinewave, after that nothing. The 2 ns after that, peaks get applied to the sampled values to simulate how the signal looks like (and how a computer would reconstruct it)
<Degi> Seems to have -3 dB at approximately 10 GHz.
<Degi> Seems to have only 20 mV compared to 40 mV at 2 GHz (with 500 mV input amplitude)
<NeroTHz> does that transistor model contain parasitics?
<Degi> 2 € 10 GHz S/H haha
<Degi> Im not sure tbh
<Degi> .MODEL BFU730F NPN(Is=59.79E-18 Bf=275.1 Nf=992.6e-3 Vaf=10.34 Ikf=24.45e-3 Ise=24.75e-15 Ne=2.024 Br=81.44 Nr=980.0e-3 Var=4.245 Ikr=3.620e-3 Isc=100.0e-18 Nc=1.578 Rb=3.32 Irb=12.17e-3Rbm=1.2 Re=1.841 Rc=50.31 Cje=70.04e-15 Vje=665.6e-3 Mje=109.9e-3 Cjc=21.67e-15 Vjc=639.9e-3 Mjc=267.9e-3 Xcjc=1.000 Cjs=298.9e-15 Vjs=360.9e-3Mjs=661.7e-3 Fc=500.0e-3Xtf=43.92 Tf=1.3236e-12Vtf=-17.68 Itf=89e-3 Ptf=75.6 Tr=1.7e-12 Eg=1.110 Xtb=0.000 Xti=3.000)
<Degi> That is the .model
<Degi> Has junction C's
<NeroTHz> yeah, perhaps it does then
<Degi> But not L apparently?
<NeroTHz> it´s probably the raw die or something
<Degi> Idk, I think that circuit should work at a few 100 MHz even with some parasitics hm
<NeroTHz> yeah just because you are sampling at 100 MHz doesn´t mean your circuit is working at 100 MHz, you still have much higher frequency content
<Degi> In the image its sampling at 80 GS/s
<Degi> But IRL I think it should work to at least a few hundred MHz BW if it does 10 GHz in simulation
<NeroTHz> perhaps
<NeroTHz> I have little feel with the bandwidths discretes can achieve
<Degi> Hm we could dissolve the packaging and bond the chips ourselves
<NeroTHz> I mean just go get dies from one of the many sellers that give you dies :p
<azonenberg> Lol
<azonenberg> NeroTHz: you also have wire bonders and a VNA that costs more than my house
<NeroTHz> hey Degi was the one who brought up bonding today ;p
<monochroma> bondage?
<NeroTHz> don´t give me ideas
<Degi> azonenberg: Do you have a variable phase shifter (for example cable with bad stability), or can break out 2 serdes channels or can make a sinewave phaselocked to a serdes channel?
<Degi> Protip: Don't do a FFT in LTSpice when you have a simulation with 161 runs
<azonenberg> Degi: I can probably rig up two serdes channels. it's not sinewave output though
<Degi> Neat
<azonenberg> i could also probably rig up something with a delay line if i had some time to set it up
<Degi> Huh, apparently I have been using one of the transistors as a capacitor
<Degi> What the hell did I design there... Okay that apparently reduced working frequency somewhat but greatly increased output amplitude
<Degi> Yes, now I get 100 mV at 2 GHz and up to 30 mV at 10 GHz, but now it has 60 ps FWHM sample time
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<Degi> So many parameters which only work in a certain range... Like theres 2 resistors and the pulse width which need to be in a certain range to get output
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<Degi> It seems to be kinda noisy in an ideal simulation, though it might be sampling error noise
<Degi> TFW 4 ns * 161 steps of simulation at 1 ps... Now the noise is gone.
<Degi> I got to -6 dB at 10 GHz vs 2 GHz
<Degi> 2 vs 10 GHz with same ampltiude
<Degi> -3.6 dB, this needs some iterative optimization
<Degi> So theres like 5 variables to optimize, but I think this circuit can work pretty okay
<Degi> And leakage on a 1 pF capacitor huh
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