azonenberg changed the topic of #scopehal to: libscopehal, libscopeprotocols, and glscopeclient development and testing |,, | Logs:
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<azonenberg> ok new oshpark attenuator test board is here
<azonenberg> Preparing to test it
<azonenberg> Defintitely better, the only question is how much
<azonenberg> ok so, simulation not accounting for ENIG losses... S21 at 2 GHz, -21.47 dB with close spacing and -23.24 with wide spacing
<azonenberg> at 4 GHz, -23.72 and -27.35
<azonenberg> (this is netlist sim only)
<azonenberg> So that's an improvement of 1.77 dB @ 2 GHz and 3.63 dB @ 4 GHz
<azonenberg> Actual measurements: at 2 GHz, -23.6 and -24.07 , so about half a dB better
<azonenberg> At 4 GHz, -26.69 and -28.67
<azonenberg> so 1.98 dB better
<azonenberg> interestingly out to ~1 GHz i see almost no difference in the curves
<azonenberg> So while it is better, it's not better by as much as the simulation would predict
<azonenberg> The -3 dB bandwidth is only about 160 MHz higher than the old board
<azonenberg> now, this is on an oshpark board so not perfectly impedance tuned etc
<azonenberg> And that was with a 50 ohm terminator bodged across the GCPW
<azonenberg> Interestingly it looks like there was a slight dip in the response from 1-3 GHz
<azonenberg> I have some guesses as to what might have caused that
<azonenberg> aside from that it's tracking the sims well. I'm definitely on the right track
<azonenberg> Probably gonna do one more attenuator board with the resistors even closer together
<azonenberg> Because if you eliminate that big dip there's a truly massive improvement
<azonenberg> NeroTHz lain tnt monochroma
<azonenberg> red/blue = sim old/new, cyan/pink = VNA old/new
<azonenberg> I'm blaming the dip on the new board on soldering at this stage, i had some paste print issues and some of the joints arent looking great
<azonenberg> Gonna try and do one more test board where the resistors are basically touching
<azonenberg> I have concerns about that from a reliability/manufacturing perspective but i think if i put a tiny drop of epoxy between them it will help mitigate cracking etc
<azonenberg> and if nothing else it will let me collect more data to confirm this hypothesis\
<lain> :o
<azonenberg> lain: what do you think, am i on the right track?
<azonenberg> The sims obviously have less loss b/c they're not modeling copper roughness or ENIG losses. But those should be constant from layout to layout
<lain> seems like it yeah
<azonenberg> So now the question is how close to go
<azonenberg> The FC0402 datasheet says 1.067 +/- 0.203 mm as the package dimension
<azonenberg> So the max material dimension is 1.27 mm
<azonenberg> That said, i measured the ones on my board as very close to 1.0 mm
<azonenberg> 1.02 was the best measurement i could come up with
<azonenberg> Soo if i wanted to live dangerously i could play fast and loose with the tolerances
<azonenberg> and accept the risk that if i have a few parts at the max material dimension next to each other it wont work
<azonenberg> Binning parts would not be unreasonable for a high precision application like this... thoughts?
<azonenberg> The test board i have right now is 1.35mm pitch which is 80 microns of clearance at the max material dimension, 486 microns at min material, and 330 microns at the measured actual component size
<azonenberg> I'm debating bringing the pitch down to say 1.1 mm which would be 170 um of interference at max material, 80um at the measured typical, and 236 at min
<azonenberg> i.e. if i have two parts at max material they will have 170um of overlap, so it wont fit
<azonenberg> but if i have a big part at the end of the array, or a big between two average/small, i'm fine
<azonenberg> visually, looking at all of the boards i've done to date, they're very consistent and close to 1.0 mm in actual size
<azonenberg> lain: any input on this?
<lain> it sounds like a reasonable experiment
<lain> and I feel like it'd probably work out in your favor, statistically, in the long run
<azonenberg> That's my thought too
<azonenberg> Worst case i have to bin the resistors, take the top sigma or so of the tolerance range and isolate them
<azonenberg> then either discard them or intersperse them with the rest
<lain> yea
<lain> you can always offload them as "bought excess, unused" near to cost too in the absolute worst case that they're somehow not useful to you ever
<lain> though I suspect that's unlikely
<azonenberg> if i have to throw away 10% of my resistors, even if they're $2 each
<azonenberg> and i doubt the actual number would be anywhere close to 10%
<azonenberg> I mean honestly given how much i'm spending on tip and ground accessories
<azonenberg> that would increase the cost of a probe by less than a dollar
<azonenberg> The other problem i have, which i believe was the cause of the weird dip from 1-3 GHz as i cant think of many other explanations, was poor solder paste release
<azonenberg> i had to touch up paste on several points
<azonenberg> i think i made the apertures just a little too small
<azonenberg> I may try and add a little paste and reflow this board again but it's probably not worth the effort
<azonenberg> I know what i need to kno
<azonenberg> know*
<lain> :3
<azonenberg> we don't need no stinkin' courtyard
<lain> lol
<azonenberg> Sonnet is churning away simming this layout now
<azonenberg> we'll see how it compares to the previous one
<azonenberg> This entire board fits comfortably in ~1.2 GB of ram which is well under the 2GB cap for gold
<azonenberg> ... whoah
<azonenberg> lain: it seems like there is an exponential improvement as the gap gets smaller
<lain> :o
<azonenberg> red and blue traces are sim of first and second gen board designs as fabbed
<azonenberg> black is sim of third gen design
<azonenberg> Red trace is 2mm pitch (so 1mm spacing)
<azonenberg> Blue trace is 1.35mm pitch, so 350um spacing
<azonenberg> Black trace is 1.1mm pitch, so 110 um spacing (that's component body to body assuming 1.0mm package size)
<azonenberg> so even though red to blue is a much bigger change than blue to black, blue to black shows a much bigger improvement in S21
<azonenberg> And other than the little dip that i suspected is bad soldering on the pink trace, the pink to cyan seem to be about the same spacing as red to blue
<azonenberg> with the delta being due to ENIG losses
<azonenberg> which means if i fab this new board i should see a massive improvement. Also the dip at ~5.5 GHz in sim is not present IRL and is currently unexplained
<azonenberg> it's a modeling artifact but i don't yet know the origin of it
<_whitenotifier-3> [starshipraider] azonenberg pushed 2 commits to master [+0/-0/±2]
<_whitenotifier-3> [starshipraider] azonenberg 9d81842 - Started v1.1 probe design with closely spaced resistors
<_whitenotifier-3> [starshipraider] azonenberg e8ff0ee - New closer spaced variant
<azonenberg> Sim is still running but it looks like 4x 100 + 50 beats 100 + 4x 75 + 50
<azonenberg> with the new closer spacing
<azonenberg> The difference is small compared to the previous rev jump, but it also will save a buck or two off the BOM. So better performance AND lower cost seems like a win-win
<_whitenotifier-3> [starshipraider] azonenberg pushed 1 commit to master [+6/-0/±5]
<_whitenotifier-3> [starshipraider] azonenberg 4823061 - New attenuator test rev with 5 resistors
<azonenberg> I'm actually gonna try to go down one more, to 200, 2x 100, 50. This peaking might actually help null out losses elsewhere in the system
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<_whitenotifier-3> [starshipraider] azonenberg pushed 1 commit to master [+1/-0/±2]
<_whitenotifier-3> [starshipraider] azonenberg 1f051cd - Updated attenuator test with 4 overlapping resistor footprints
<azonenberg> and cyan trace is the latest iteration
<azonenberg> I still dont know where that dip at 5.25 GHz is coming from, it's not in the VNA data. Neither is the other dip at 1.75
<azonenberg> But the overall shape of the curve matches the measurements
<azonenberg> and this is a HUGE improvement over either of the as-fabbed designs
<azonenberg> I think i'm about ready to send this one to fab and see if it's half as good as the sim says
<_whitenotifier-3> [scopehal] smunaut opened pull request #231: Fix ffts include path -
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<Degi> How does the layout look like now? That looks real flat
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<azonenberg> Degi: that cyan trace is 200, 100, 100, 50 ohms in a series string at 1.1mm pitch
<azonenberg> so the packages are almost touching
<azonenberg> at the nominal component side there's like 50-100um of courtyard and if two resistors hit the max size of the tolerance band they'll actually collide and it wont work
<azonenberg> but i'm taking that risk and i'm willing to occasionally throw out a part at the end of the tolerance band
<Degi> Ah neta
<Degi> *neat
<azonenberg> the current actual probe and attenuator test board are 2mm pitch so 1mm spacing at nominal size
<azonenberg> So at this point i'm sufficiently happy with the results that i'm probably going to simulate a full probe board with this layout of the attenuator
<azonenberg> then if it works well, order both a probe and an attenuator test at oshpark
<miek> have you thought about revisiting a config with fewer resistors, now you've got better simulations, tip setup, sma launch, etc.?
<azonenberg> Yes
<azonenberg> The black trace in that plot is my best 6-resistor design
<azonenberg> pink is five and cyan is four
<azonenberg> I may even try going down to 3 now. The original sims that led me to go to six were inaccurate and i made the wrong decision based on them
<azonenberg> Basically, while it is true that the higher valued resistors like 100/200/1K have peaking due to shunt capacitance, you also lose high frequency signal elsewhere in the system due to various factors, and the stubs between resistors
<azonenberg> so the combination of the peaking and less stubs actually helps flatten the response
<azonenberg> My original simulations assumed that a 1mm stub was insignificant at low single digit GHz and both simulation and VNA measurements now confirm this is absolutely not the case
<azonenberg> The confounding factor was overshoot i saw early on during prototype testing that i falsely assumed was the result of high freq peaking
<azonenberg> it was actually, i believe, an artifact of measuring a broadband pulse with a low bandwidth instrument
<azonenberg> and i think my response was flatter than i thought it was back then
<azonenberg> But confounded by reflections off the old SMA
<miek> the thing i've been wondering about is whether it's a problem to have this length of 50ohm-tuned gcpw around the attenuator that's not really at 50ohm until the end. maybe it's better to do that step in one resistor?
<azonenberg> That *would* have huge peaking
<azonenberg> I tried
<miek> the config i see a lot on the front of fancy active probes is a small (~100ohm) damping resistor as close as possible to the tip, then a single higher value for the attenuator, then 50ohm line from there
<azonenberg> Pulling the copper back around the resistor might help
<azonenberg> I'm also going to be pulling back around the tip to reduce parasitic input C to ground
<azonenberg> that should not change response a ton, but will give higher input Z due to less shunting of the signal to ground bypasing the probe
<electronic_eel> have you tried using fine grit sandpaper to sand down the resistors a bit? then you can put them even closer ;)
<azonenberg> lol
<azonenberg> that sounds like a terrible idea
<azonenberg> also, early simulations of 200+200+50, the shortest string i can do with stock Vishay resistor values, are even flatter. Still running
<azonenberg> I think the combination of ENIG losses, the bad SMA, and lower bandwidth measurement capabilities meant i was totally on the wrong track before
<electronic_eel> the resistive part on these resistors is at the top and they have a conductive part at the ends going down and the pad just on the bottom?
<azonenberg> No
<azonenberg> the resistive part is on the bottom
<azonenberg> they're basically 2 pin LGAs
<azonenberg> the alumina substrate is just for mechanical support
<azonenberg> it's nichrome film with ENIG pads for soldering at either end
<azonenberg> this is also why they're only 1/20W rated
<azonenberg> Because they can't cool as well as a normal wraparound version
<electronic_eel> hmm, then it won't change the resistance if you shave off a part of the pad
<azonenberg> Correct
<azonenberg> it's possible to do
<azonenberg> At this stage i dont think it's necessary
<azonenberg> Simulations are looking *really* nice at this point
<miek> mill a pocket and mount them alternating pad to pad :p
<azonenberg> incidentally, since this new layout uses a 200 as the highes valued resistor instead of a 100
<azonenberg> the max voltage will drop
<electronic_eel> miek: can't you get pcbs that have such pockets milled in already?
<electronic_eel> obviously not with the $2 jlcpcb prototype pcbs
<azonenberg> Max current through the probe is dropping from 22 mA to 15.8 mA, which comes out to a max of 7.905V instead of the 10Vrms I have now
<azonenberg> So it's not a huge drop ion usable range
<azonenberg> in*
<_whitenotifier-3> [scopehal] azonenberg closed issue #230: Wrong FFTS include path -
<_whitenotifier-3> [scopehal] azonenberg pushed 2 commits to master [+0/-0/±8]
<_whitenotifier-3> [scopehal] smunaut 863ee1d - Fix ffts include path From how FindFFTS.cmake works, LIBFFTS_INCLUDE_DIR will already include the ffts/ component. Fixes #230 Signed-off-by: Sylvain Munaut <>
<_whitenotifier-3> [scopehal] azonenberg d034968 - Merge pull request #231 from smunaut/fix-ffts Fix ffts include path
<_whitenotifier-3> [scopehal] azonenberg closed pull request #231: Fix ffts include path -
<_whitenotifier-3> [starshipraider] azonenberg pushed 1 commit to master [+1/-0/±2]
<_whitenotifier-3> [starshipraider] azonenberg 439e0e1 - Attenuator test with 3 resistors
<azonenberg> There we go
<azonenberg> 1.1 dB down in simulation at 6 GHz :D
<azonenberg> again, attenuator only not the full probe. and the oshpark test board will have another bunch of loss on top of that from the ENIG
<azonenberg> But this is a massive improvement over what i have now
<azonenberg> next step i think is to do a model of the entire probe with 200-200-50 at close spacing
<electronic_eel> the full sonnet makes a huge difference
<azonenberg> Yes
<azonenberg> I'm 100% sold
<azonenberg> just a question of how fast i can come up with the funds
<azonenberg> all of the attenuator test boards fit in gold, the full probe would be tricky to model without pro because it's so big but i might be able to segment it
<electronic_eel> can you take the demo license file and switch the date on your pc back? or does it need online connection for the license verify?
<azonenberg> and the multithreaded solver is also huge
<azonenberg> It's flexlm and i reverse engineer software for a living. I have zero doubt i could crack it if i wanted to
<azonenberg> but i can't crack a support contract
<azonenberg> That, and i actually want to support these guys, they're a small company and do great work
<azonenberg> they're not like cadence or synopsys
<electronic_eel> do you want to start working on the flatflex solder-in probes you wanted to do while you still have the demo?
<azonenberg> Thinking about it, but higher priority is any tweaks to MAXWELL i might need
<azonenberg> I need to get that ready to send out asap
<azonenberg> also i still have to print out the cal cert and do the customs form for your probes
<azonenberg> sorry, you're one of two i havent mailed yet
<electronic_eel> you need to get sonnet ultra (and a hpc cluster) to sim MAXWELL ;)
<azonenberg> They actually have an "emCluster" feature available with pro
<azonenberg> Pro can use up to 64 threads on a single machine within a single frequency
<azonenberg> the clustering tool runs one frequency on each compute node
<azonenberg> so you can get embarrassingly parallel scaling across bands
<azonenberg> But you need a pro seat for every compute node
<azonenberg> which puts it out of my reach for the foreseeable future
<azonenberg> that said, performance is quite good on my dual xeon workstation using the solver on 32 threads'
<electronic_eel> oh, so it is not the rack full of epycs that is expensive, but the licenses...
<azonenberg> i'm not looking forward to being back on one thread
<azonenberg> Gold has the capabilities to model almost everything i'm doing (mostly multilayer via transitions and really huge designs are the limits)
<azonenberg> But it's still single threaded
<azonenberg> I think i can afford gold soonish but pro will likely have to wait till next year at the soonest
<azonenberg> I need a hpc cluster for many reasons though :P
<Degi> Hm if you buy gold and then pro, does it have the same total price as buying pro now?
<azonenberg> Degi: if you upgrade with an active support contract, they credit the cost of the lower edition to the higher one
<azonenberg> so you can go from basic to silver to gold to pro and pay the same amount as if you had just got pro first thing
<azonenberg> however you get 4 years of support by going piecewise instead of 1 :p
<azonenberg> so its actually a better deal lol
<azonenberg> At this point i am planning to upgrade from basic to silver late this year, then gold as soon as budget permits
<azonenberg> pro is on the roadmap but is a ways out
<Degi> Neat
<azonenberg> proposed new business end of the probe
<azonenberg> copper pulled back from the tip socket because i dont actually need 50 ohm Z before the attenuator, and extra capacitance hurts
<azonenberg> and the new 3 resistor closely spaced attenuator
<azonenberg> then some nonfunctional copper outside the CPWG area removed to prevent any chances of ground plane resonances
<azonenberg> Now simulating that probe. 3.5 GB at the medium mesh resolution so beyond what gold can simulate - but small enough that i could probably fit it in gold if i split the CPWG in half and simmed it in two blocks
<azonenberg> So far it's only done 2 freqs but it's 9.4 dB better than the last revision at 10 GHz
<azonenberg> So i have high hopes
<miek> ooh, nice
<Degi> Oh neat
<Degi> Can you do a Z plot? And how long do simulations usually take?
<azonenberg> Z plot?
<azonenberg> you mean impedance vs freq?
<Degi> yes
<azonenberg> Yeah thats trivial
<azonenberg> and sim time goes up quadratically with the number of mesh cells. This sim is 3.5 GB of RAM and using 19K mesh cells
<azonenberg> On 32 threads it's taking about 5-6 minutes per frequency
<Degi> oh, how many frequencies do you have
<azonenberg> Hard to say. it's doing an adaptive sweep
<Degi> Ah
<azonenberg> so basically it starts by doing the beginning and end of the range, then a bunch in between
<azonenberg> when it sees points with a high gradient it does more freqs around them to find the shape more precisely
<azonenberg> areas with little change get done at lower resolution
<azonenberg> then it fits a curve to the result
<azonenberg> you can also do a simple linear sweep but that usually takes massively more time
<azonenberg> Generally speaking most of these runs i've done have ended up needing something along the lines of 20 freqs
<Degi> Yes thats a good idea
<azonenberg> yeah pretty much every EM sim tool has this, although they all have different names for it
<azonenberg> So this sim is actually showing about 3.1 dB of peaking at 4 GHz for the full probe. But i think that won't be a problem due to losses from tips and such
<azonenberg> i think it will actually help flatten out the response
<azonenberg> There is also a weird resonance in the previous sims around 1-1.5 GHz that doesnt show up in the real board
<azonenberg> So there's definitely some artifacts i need to figure out
<azonenberg> So this new design is showing massively higher input impedance too
<azonenberg> Pulling the ground back from the tip seems to have helped. A lot
<azonenberg> I think i have a winner here, and if it turns out i have overshoot after losses elsewhere i can always move the resistors a bit further apart to flatten it out
<miek> excellent :)
<azonenberg> But i wish i knew where some of these resonant spikes i'm seeing were coming from
<azonenberg> because they're not there on the real board
<azonenberg> the good news is most of these artifacts are the same from sim to sim, so if i run several with different parameters i can look at the deltas and still get a good idea of what the hardware is gonna do
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