00:20 <mkk__> [Patrick Van Oosterwijck, skywater-pdk] @Tim 'mithro' Ansell I have a question about repo structure. I'm intending to start a shared Github repo for power management related blocks I will be working on with a couple of collaborators. Each IP block (bandgap, low side driver, high side driver, LDO) would inhabit a subdirectory in the repo. If we make it for the shuttle, there would also be a "tapeout-1" or similar directory for t

01:09 <mkk__> [Tim 'mithro' Ansell, skywater-pdk] I would suggest using branches

12:39 <mkk__> [FatsieFS, skywater-pdk] @Adrian Freed The area of a nand gate is typically tranformed to a value xxx kgates/mm2. For 0.13um 200-300kgates/mm2 seems good values.

12:39 <mkk__> For comparison I think it is also good to give the highest metal layer used in the cells. AFAICS the OSU seem to use metal1 for internal cell routing as the SkyWater libs only use metal1 for the power rails. This is important to estimate the overhead needed for P&R.

12:39 <mkk__> Sometimes a difference is made between raw gate density and effective gate density where raw is based directly on area of NAND2 and effective taking into account the overhead needed for P&R. The latter is not fixed as it depends on the design and the P&R flow used.

17:01 <mkk__> [Adrian Freed, skywater-pdk] yes, that raw/effective distinction is important. If a few representative designs can be agreed on, the effective numbers can be made by running them through many libraries. This would be a useful guide metric (along with the power and area numbers).

17:31 <mkk__> [Adrian Freed, skywater-pdk] I updated with raw kgates/mm2. The densities are a bit lower than you suggested perhaps because the drawn transistor length is 150nm not 130nm?