<lkcl>
ah excellent, i was wondering if this channel existed :)
<lkcl>
mithro: we had a meeting yesterday with Staf from Chips4Makers and with LIP6.fr to organise for a Dec 2 deadline on Euro-Practices 180nm MPW, it went very well
<lkcl>
however one thing came up that we really should consider a 2nd iteration in around 6 months time.
<lkcl>
i'm familiar with the 25 mm^2 area (we meet that), we can manage with the flip-chip (by using HyperRAM for the pins)
<lkcl>
what are the "practical issues" involved? what's the "process"?
<lkcl>
what do we need to know that we don't know, basically :)
<lkcl>
the license for LibreSOC is LGPLv3+ (NOT Affero GPLv3 which is a no-no)
<lkcl>
is that one a misunderstanding (on my part), there's a mandatory RISC-V "supervisor" core that has to go on all dies?
<lkcl>
Staf has created a really good JTAG HDL (which is silicon-proven i think) that can do IOpad scanning. it also includes a wishbone bridge and i've added a DMI bridge as well
<mkk__>
[Tim 'mithro' Ansell, skywater-pdk] realname: Yes there is a mandatory RISC-V "supervisor" but you can 100% ignore it if you want
<lkcl>
mkk: ok brilliant. interesting. out of curiosity will it be on its own JTAG bus so you're able to scan it "just because"? :)
<lkcl>
that would allow you to like, at least test-prove the relationship with skywater
<lkcl>
other questions on the check-list:
<lkcl>
* because PLLs are normally under NDA, a Professor from LIP6 is doing a (180nm) PLL for us. is there one that's already entirely libre-licensed as part of the 130nm PDK or should we ask him to do it?
<lkcl>
* is LPLv3 licensed code ok (i mean, it should be, however we do need to check)
<lkcl>
* in practical terms, if we use Alliance / Coriolis2 from LIP6 how would that be "integrated" with the RISC-V "supervisor"?
<lkcl>
would we provide the source code plus a build script and you do it?
<lkcl>
or
<lkcl>
do we provide a GDS-II file with "a hole where the RISC-V supervisor goes"
<lkcl>
or
<lkcl>
other
<mkk__>
[Tim 'mithro' Ansell, skywater-pdk] It's more that your GDS-II file goes into a hole that exists in the harness
mkk__ has left #skywater-pdk [#skywater-pdk]
mkk__ has joined #skywater-pdk
<lkcl>
okaay, nice. that would work very nicely
<lkcl>
i get the impression you're very busy :) simple questions, then
<lkcl>
is LGPLv3+ HDL ok?
<mkk__>
[Riking28, skywater-pdk] Apache2 is the only one locked in as definitely confirmed OK. The only other news we have is that GPLv3 is likely accept
nickoe has quit [Remote host closed the connection]
nickoe has joined #skywater-pdk
<lkcl>
riking_: and of course we can "upgrade" LGPLv3 to GPLv3. we picked LGPLv3 specifically though so that it could be combined with proprietary libraries
<lkcl>
but if enhancements are made to the core it's required to provide the source code.
<lkcl>
it's a nice half-way-house that allows us to use proprietary HDL
<lkcl>
and take advantage of LGPL and GPL peripheral HDL
<lkcl>
but also if there is any company that wants to license our work under alternative licenses, they'll have to come to the Libre-SOC Foundation to negotiate.
<lkcl>
if we release the code - right now - under a permissive license we instantly lose that possibility.
<lkcl>
the other reason for adding standard "open source" licenses - BSD, MIT, CC - is of course that code on opencores.org and other locations is under those licenses.
<lkcl>
people are hardly going to rewrite silicon-proven / FPGA-proven libre/open HDL that's "not on a list of licenses"!