<mkk__>
[Tim 'mithro' Ansell, skywater-pdk] lkcl: Goal is to eventually be able to do this for any standard cell library
<mkk__>
[Tim 'mithro' Ansell, skywater-pdk] lkcl: Generally we are trying to reuse a lot of tooling everywhere
<lkcl>
have you heard of Staf Verhaegen? from Chips4Makers? he's developing a version of sxlib that will be about a 35% reduction in area from the "usual" libre version of sxlib
<mkk__>
[Tim 'mithro' Ansell, skywater-pdk] I talk to Staf about once a month
<lkcl>
oh good! :)
<lkcl>
we'll be testing out his iopads and cell library for a dec 2 180nm tape-out
<lkcl>
is there a 2nd 130nm skywater run planned already or is it conditional on seeing how this one goes?
<Lofty>
I have a worrying suspicion that if I want to super-optimise this FPGA I'll probably need custom cells
<Lofty>
I do *not* fancy my chances in ASIC design
<mithro>
Lofty: Yes, the OSU team could help you there
<Lofty>
The good news is that I have a semi-automated flow for getting cell timings and putting designs through ABC9
<Lofty>
And using the Yosys sta command to get a rough logic delay estimate
<mithro>
So if I understand correctly Xilinx Virtex-II was done with 130nm technology
<Lofty>
The hs library is surprisingly competitive
<Lofty>
Of course it draws a lot more power than, say, hd or lp, but a LUT6 design with hs has competitive timings to a 28nm FPGA like the Cyclone V or Xilinx 7 Series
<Lofty>
Power draw doesn't bother me that much, at least.
<mithro>
Something seems a bit weird there -- I guess you are not modeling the interconnect delay yet?
<Lofty>
This is LUT input to LUT output timings
<Lofty>
Same for the 28nm LUTs as it is for the 130nm LUTs
<Lofty>
Based on those timings - obviously the routing delays are a factor - LUT5s seem most optimal here
<mithro>
Are these facturable LUTs?
<Lofty>
Presently no, but I intend to experiment with fracturable LUTs.
<mithro>
Lofty: It's basically a flip flop you can inject into your design in place of a traditional flip flop. You then connect them together to create a giant shift register to let you set the flip flop values to a given state