<mkk__>
[Tim 'mithro' Ansell, skywater-pdk] @Adrian Freed As FatsieFS pointed out there is "Sometimes a difference is made between raw gate density and effective gate density where raw is based directly on area of NAND2 and effective taking into account the overhead needed for P&R." -- that is actually quite important -- IE 60% is pretty common for that number
<mkk__>
We are working on our first tapeout of an SoC through the shuttle program with skywater pdk using OPENLANE.
<mkk__>
Where are these variables being set up?
<mkk__>
I needed a little guidance regarding the location of the variables like LIB_MIN, LIB_MAX etc. which are not in the configuration/synthesis.tcl.
<mkk__>
[Wajeh ul hasan, skywater-pdk] Hi @Tim 'mithro' Ansell, this is Wajeh (RA at MERL, Pakistan). We really appreciate the initiative by Google +efabless and skywater.
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<mkk__>
[Sylvain Munaut, skywater-pdk] @Wajeh ul hasan I think they're setup in the cell library config file that's in open_pdk