14:45 <synaption[m]> Can someone point me in the direction of some documentation please. I'm just wondering if the state of any of these projects is at the point where I can control the parameters of something like a PLL straight from verilog or migen. Or is that not the intention? Where can I read more about actually using the stuff that has been opened up in the bit stream.

14:47 <bunnie[m]> If you're asking what I think you're asking to do, I don't think you need the bitfile format to control the PLL on a 7-Series. You can reconfigure a PLL using the DRP bus, which is documented and exposed.

14:49 <bunnie[m]> https://github.com/AlphamaxMedia/litevideo/blob/3bc5a24a08881c96d203d9b9244092704376d29e/litevideo/input/clocking.py#L136

14:49 <tpb> Title: litevideo/clocking.py at 3bc5a24a08881c96d203d9b9244092704376d29e · AlphamaxMedia/litevideo · GitHub (at github.com)

14:50 <bunnie[m]> corresponding firmware at https://github.com/AlphamaxMedia/netv2-fpga/blob/master/firmware/mmcm.c#L136

14:50 <tpb> Title: netv2-fpga/mmcm.c at master · AlphamaxMedia/netv2-fpga · GitHub (at github.com)

14:51 <synaption[m]> can that be configured from any of these open source tool chains? because my experience is that PLLs get configured by a vendor specific GUI block thing that generates some verilog and that is the only advisable way of doing that.

14:53 <bunnie[m]> You can write the bits into the PLL block from any open source toolchain, but the meaning of the bits is a little bit trickier. There's a little bit of code-fu required to figure them out. If you're interested in 7-series, it's fairly well documented in XAPP 888, "7 series dynamic reconfiguration"

14:55 <bunnie[m]> In particular, the optimal settings for the PLL divisors and lock filters are not well documented. However, Xilinx did publish an RTL model that computes these things.

14:56 <bunnie[m]> I've done some comparison of what the e.g. clocking wizard creates vs. what the RTL models compute. They aren't an exact match, but the performance is good enough for most scenarios

14:57 <bunnie[m]> I think it's only a real problem if you're trying to really push the edges of the capability of the PLL, like trying to lock onto a very jittery input clock or running at the extreme highs or lows of the capability.

14:58 <synaption[m]> I'm looking at your links right now, and I'm not Tim, so python has not completely eaten my brain. But it's my understanding that the litex stuff still uses vendor tools in the back end mostly.

14:58 <bunnie[m]> This is correct, the compliation for 7-series is still reliant on the Vivado toolchain

14:58 <bunnie[m]> however, that has to do with the place-and-route of the PLL, not the tuning of the PLL parameters

14:59 <synaption[m]> I think that answers the question. Do you know about any of tha lattice stuff?

14:59 <bunnie[m]> no, i am not very familiar with the lattice FPGAs.

14:59 <bunnie[m]> the ICE40 has a pretty trivial PLL and I know that works. But the ECP5 I am not sure of the status.

15:00 <daveshah> There is an ecppll tool that does pretty well and nextpnr/trellis supports all the PLL features at place-and-route level

15:00 <daveshah> some attributes might not be set optimally but there've never been any failures in the wild

15:03 <daveshah> LiteX can set up an ECP5 PLL directly, I don't know about [n]Migen

15:07 <synaption[m]> daveshah: cool. do you know where I can read more about that. I'm finding a lot about how to figure out the bit stream, but not so much about how to use it after it's figured out.

15:08 <daveshah> There are some notes in the source code, not much more than that

15:08 <daveshah> https://github.com/SymbiFlow/prjtrellis/blob/master/libtrellis/tools/ecppll.cpp

15:08 <tpb> Title: prjtrellis/ecppll.cpp at master · SymbiFlow/prjtrellis · GitHub (at github.com)

15:11 <synaption[m]> well, that's something. thanks guys

15:23 <sf-slack> <mkurc> Currently there is support for PLLE2_ADV, you can instantiate it in HDL and assign parameters in the same way as in vendor tools.

15:23 <sf-slack> <mkurc> Dynamic reconfiguration should work but has not been tested yet.

15:24 <sf-slack> <mkurc> Its for 7-series FPGAs off course

15:25 <OmniMancer> How is dynamic reconfig of PLLs exposed?

15:26 <sf-slack> <mkurc> There is a parallel interface exposed that allows PLL registers to be read/written in runtime.

15:26 <sf-slack> <mkurc> The process is described in detail in XAPP 888

15:27 <sf-slack> <mkurc> (also with some example design)

15:28 <OmniMancer> Thanks

15:35 <sf-slack> <mkurc> The documentation for the 7-series support is still work in progress but if you want to know what primitives are supported you can always check the xc7/techmap/cells_map.v.

15:36 <sf-slack> <mkurc> The file contains a mapping of cells that Yosys generates with the synth_xilinx command to those that we use for P&R

15:36 <sf-slack> <mkurc> If something is there then it is supported.

22:27 <hackerfoo> check_route takes about 7x as long as routing murax with the ROI graph, and prints a lot of warnings.

23:17 <hackerfoo> Iterating over the std::map rr_non_config_node_sets_map_ is expensive.

23:20 <hackerfoo> And the std::set find inside the loop in EdgeGroups::output_sets()

23:32 <hackerfoo> Does it make sense to add a flag to disable checking non-configurable edges? Is this check important? I guess some checking is better than none.