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[prjxray] mkurc-ant opened issue #1183: Possible instability of 047 for Zynq - https://git.io/Je5fi
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<flow>
Thank you for the amazing work! I just tried to build the LiteX SoC for one of my boards, the resulting bitstream is larger (693,607 vs 582,343 bytes) than the bitstream size I get when synthesizing my other designs (which are a lot less ambitious) might that be due to the ROM initialization? For my uploading tools I would prefer that the size of
<flow>
the bitstream is always fixed. Is there a way to force ecppack to initialize everything that is not used to 0 or some other value?
<sf-slack>
<kgugala> hi @flow which FPGA are you targeting?
<flow>
the ecp5 with 25k logic elements
<flow>
LFE5U-25F-6BG256C
<daveshah>
Yes, this is because of initialised RAM
<daveshah>
There is no option like that at present
<daveshah>
But you can safely pad bitstreams with 0xFF at the end if that helps
<flow>
oh thats good to know and fixes my problem, Thank you!
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<hackerfoo>
Has anyone seen an error like this? make[4]: *** No rule to make target '../xc7/archs/artix7/devices/xc7a50t-virt/xsltproc', needed by 'xc7/archs/artix7/devices/xc7a50t-virt/arch.merged.xml'. Stop.
<hackerfoo>
`make all_conda` doesn't help.
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<_whitenotifier-5>
[symbiflow-arch-defs] rodrigomelo9 opened issue #1243: parse_pdf_modules.py seems to be not working - https://git.io/Je5lX