15:06 <_whitenotifier-5> [vtr-verilog-to-routing] acomodi opened issue #350: Branch: place-constraints - https://git.io/Je9Zf

18:00 <_whitenotifier-5> [symbiflow-arch-defs] litghost opened issue #1215: Try integrating capnp rrgraph to symbiflow-arch-defs - https://git.io/Je9W4

19:14 <hackerfoo> https://github.com/SymbiFlow/vtr-verilog-to-routing/tree/wip/lookahead_sampling2

19:14 <tpb> Title: GitHub - SymbiFlow/vtr-verilog-to-routing at wip/lookahead_sampling2 (at github.com)

19:31 <hackerfoo> litghost: Does it make sense to put a lot of effort into clock routing (e.g. two phase routing?) Do you think that it is likely to block future work?

19:32 <litghost> hackerfoo: two phase routing is a good idea, and we should add it

19:32 <litghost> hackerfoo: Whether the 2 phase router is what we want, is unclear

19:33 <hackerfoo> I'm currently trying to speed up check_route, but I don't think this is very important.

19:34 <hackerfoo> Improving clock routing will likely take a while, unless the current 2 phase router works out.

20:04 <litghost> nah, we just disable check_route