<heijligen>
kgugala: the axi ps7 example is now working. Thanks
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<_whitenotifier-5>
[sv-tests] mithro opened issue #548: Add Verilator in multiple modes - https://git.io/Jvva4
<_whitenotifier-5>
[sv-tests] mithro opened issue #549: Some basejump_stl files are abstract base classes and should be marked parse only - https://git.io/JvvaK
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<hackerfoo>
Any suggestions on how to identify the output from a BUFG that should be the root of a clock network in VPR?
<hackerfoo>
The general idea is to route the part before and after a high fanout net in two stages, so I need to identify where the fanout happens, which should be the output of a buffer.
<hackerfoo>
And so I think it makes sense to start with BUFGs.