08:29 <mangelis> hi

08:29 <mangelis> is there some way to debug (other than running the actual bitstream on device) what yosys/nextpnr generates?

08:30 <mangelis> i have a case where things work weirdly on device, but seem to be okay when simulated on verilator

08:34 <sf-slack1> <mkurc> What FPGA are you targeting ?

08:43 <mangelis> ECP5

08:48 <sf-slack1> <mkurc> For ECP5 I can't tell. But for XC7 we have a tool called fasm2bels that can basically decode a bitstream to verilog.

09:05 <daveshah> No, there isn't anything like this for ECP5

09:29 <mangelis> i wonder write_verilog command would work on yosys

09:30 <daveshah> Yes, that tests the Yosys side at least

09:31 <sf-slack1> <mkurc> Provided that you have proper simulation models for cells that are used by the synthesized design.

09:32 <sf-slack1> <mkurc> Most of them should be part of Yosys cells_sim.v library file for ECP5.

10:31 <mangelis> ah does write_verilog also output code that implements the luts too?

10:33 <ZirconiumX> If you run it after synth_ecp5, yes

10:37 <mangelis> are there any good netlist viewers for linux?

10:38 <ZirconiumX> Depends what you mean by netlist viewing. You can use `show` to dump a massive GraphViz plot

10:38 <abeljj[m]> Check out opencircuitdesign by TimEdwards

10:38 <abeljj[m]> mangelis:

10:39 <abeljj[m]> *

10:39 <mangelis> just wondering about those write_ commands that write netlists that what should be used to view those files

20:28 <mangelis> okay, since write_verilog didn't show anything suspicious, i found the issue was actually in the other connected device. thanks for the tips!