<Xiretza>
daveshah: nextpnr-xilinx routing has become incredibly slow, basically not finishing at all for anything larger than a few gates, is that known?
<daveshah>
Xiretza: there was a change relating to some IO but it shouldn't add more than a second or so
<daveshah>
Have you rebuilt the database after updating?
<Xiretza>
daveshah: prjxray/database hasn't updated since december, but I did rerun bbaexport/bbasm, yes
<daveshah>
Yeah that's what I was checking
<daveshah>
attosoc.sh still routes fine for me, about 18s which is similar to before
<daveshah>
You can try the router2 branch, that is a new experiemental router that is usually much faster
<Xiretza>
daveshah: I did try that, but it errored because it couldn't find a route - maybe I just hadn't rebuilt the db though, will try that now
<daveshah>
If it hits an error then that needs to be looked into - router2 will be the default for xilinx very soon
<Xiretza>
daveshah: router2 managed to route one design now, but another (that didn't ever finish with latest xilinx branch) gives "Failed to route arc 0 of net [...]".
<daveshah>
Can you post the design?
<daveshah>
also, curious how quickly did old nextpnr route it? how big is it?
<Xiretza>
it's just the IO part of a UART (state machine, shift registers, parity), so not very
<daveshah>
My guess is that somehow the design is being placed in an unrouteable way
<Xiretza>
what would you like, write_verilog output, json? the actual sources are VHDL