10:09 <mithro> The images in https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/1090 looks pretty

10:09 <tpb> Title: Improve VPR Graphics Router Expansion Visualization by kmurray · Pull Request #1090 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com)

10:15 <_whitenotifier-3> [yosys-symbiflow-plugins] tmichalak opened issue #6: Travis: Add travis utility functions to for adding sections instead of echos - https://git.io/JvOuE

14:25 <mithro> acomdi: Quick - click the merge button! -> https://github.com/SymbiFlow/symbiflow-arch-defs/pull/1267/files

14:25 <tpb> Title: Add penalty cost switch to avoid wrong routes by acomodi · Pull Request #1267 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com)

14:26 <sf-slack1> <acomodi> @mithro Done

15:02 <mithro> Looks like kmurray is back now

15:42 <sf-slack1> <acomodi> litghost/mithro: By looking at the dcp, placement is kinda spread across many clock regions, while the minitest occupies only one + a little portion of the adjacent clock regions

15:42 <sf-slack1> <acomodi> I wonder whether it would be worth adding a way to constrain the placer to use a specific area. I have looked through the code and it should be fairly straightforward

15:42 <litghost> acomodi: The placer has a tuning parameter that changes wirelength vs timing strength

15:43 <litghost> acomodi: You could try switch the placer to a heavier wirelength focus, and see what happens

15:44 <sf-slack1> <acomodi> litghost: Ok, I'll try that, thanks

15:57 <mithro> acomodi: What does vivado say now when you back import into it

16:05 <sf-slack1> <acomodi> mithro: so, when I open the dcp it actually says nothing, but I can generate a series of reports I guess

16:05 <sf-slack1> <acomodi> Like power, timing and so on

16:19 <sf-slack1> <acomodi> mithro: here are the reports created from the dcp (util, power and timing) https://file.io/KC2FqI

16:25 <mithro> acomodi: That is a 404 for me

16:27 <sf-slack1> <acomodi> mithro: Ya, this should work: https://filebin.net/0q3nqcvv67vqjymw

16:27 <tpb> Title: Filebin :: bin 0q3nqcvv67vqjymw (at filebin.net)

17:09 <mithro> acomodi: That timing report appears to be missing a lot of things

17:10 <mithro> acomodi: I would expect something that looks more like this -> https://github.com/timvideos/HDMI2USB-firmware-prebuilt/blob/master/archive/master/v0.0.4-584-g2011661/arty/net/vexriscv.linux/gateware/top_timing.rpt

17:10 <tpb> Title: HDMI2USB-firmware-prebuilt/top_timing.rpt at master · timvideos/HDMI2USB-firmware-prebuilt · GitHub (at github.com)

17:13 <mithro> acomodi: You should see something like https://github.com/timvideos/HDMI2USB-firmware-prebuilt/blob/bf8ee7bf8ec3569980b02ab39c9700bf4b9ce5a9/archive/master/v0.0.4-584-g2011661/arty/net/vexriscv.linux/gateware/top_timing.rpt#L5078-L5120

17:13 <tpb> Title: HDMI2USB-firmware-prebuilt/top_timing.rpt at bf8ee7bf8ec3569980b02ab39c9700bf4b9ce5a9 · timvideos/HDMI2USB-firmware-prebuilt · GitHub (at github.com)

17:13 <sf-slack1> <acomodi> mithro: Yeah, I am trying to get more info there, but it seems to output one path only. The `report_timing_summary` option outputs something that does not include one single timing information (there are a bunch of N/As) and blank tables

17:14 <mithro> acomodi: https://github.com/timvideos/HDMI2USB-firmware-prebuilt/blob/master/archive/master/v0.0.4-584-g2011661/arty/net/vexriscv.linux/gateware/top.tcl

17:14 <tpb> Title: HDMI2USB-firmware-prebuilt/top.tcl at master · timvideos/HDMI2USB-firmware-prebuilt · GitHub (at github.com)

17:14 <mithro> acomodi: Are you loading the xdc file?

17:16 <sf-slack1> <acomodi> @mithro: Yep, the design checkpoint includes that

17:18 <mithro> acomodi: Great, just checking...

17:18 <sf-slack1> <acomodi> mithro: I think that we need to include reports extraction during fasm2bels

17:18 <mithro> hrm

17:18 <mithro> ?

17:19 <sf-slack1> <acomodi> I mean, when we generate the bitstream from Vivado through fasm2bels, we need also to output all the possible reports, not only the .dcp, .bit.fasm, and .bit

17:54 <litghost> I believe we might be missing "create_clocks" on some of the interior clocks

17:55 <litghost> When I wrote the initial fasm2bels tcl, there was only 1 clock, no PLL, etc

18:55 <mithro> acomodi: So - you need to put the sdc file somewhere