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<sf-slack> <garvit.gupta08> Hello everyone. I recently did my coursework in FPGA especially on artix7 basys3board ( xc7a35tcpg236-1) and I am comfortable with FPGA design and its components. I am also comfortable with verilog and C. I saw the project xray and found it exciting. A little help on additional resources which I can go through to start working on it as soon as possible.
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<IRC-Source_51> Greetings everyone !
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<ZirconiumX> Hello
<IRC-Source_51> how are you doing ?
<ZirconiumX> Not too badly I guess
<IRC-Source_51> nice :)
<IRC-Source_51> I came here seeking some help with project Xray
<IRC-Source_51> could you help me with that ?
<ZirconiumX> I don't have any experience there
<ZirconiumX> Especially since my limited energies are focused on reverse engineering Intel chips
<ZirconiumX> Not Xilinx
<IRC-Source_51> Oh I see, so you are working on a similar project for altera fpgas ?
<ZirconiumX> Kinda? We're not nearly as far as X-Ray is
<IRC-Source_51> Thats very interesting :)
<IRC-Source_51> Are you following similar methodology/approach ?
<ZirconiumX> Because I'm a student working on a lot of things
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<ZirconiumX> I have a pretty different approach actually
<Clay_1> you are working alone there ?
<ZirconiumX> You can't get nearly as low-level with Quartus as you can with Vivado
<ZirconiumX> Not entirely. There are a few people who offer advice and one person who is trying to help
<Clay_1> i see, so what is your approach ?
<ZirconiumX> I named it Project Mistral but it's less of a project and more of a hobby
<Clay_1> you have a repo ?
<ZirconiumX> I do, but it's not up to date as such
<Clay_1> I see, nice :)
<tpb> Title: GitHub - ZirconiumX/mistral: Cyclone V bitstream reverse-engineering project (at github.com)
<ZirconiumX> (the Mistral is a strong wind that blows along the south-east of France, and I thought it'd be funny since I was targeting Cyclone chips)
<Clay_1> nice trail of though
<Clay_1> are cyclone vs similar to ivs ?
<ZirconiumX> Very different
<Clay_1> i see
<ZirconiumX> But the 10GX is a die-shrink of the V, the 10LP is a die-shrink of the IV, and the Max 10 is a die-shrink of the III
<Clay_1> so the V's would be the rough equivalent of 7series ?
<ZirconiumX> Kinda yeah
<Clay_1> nice :)
<ZirconiumX> The actual technology goes back way further though
<ZirconiumX> The Arria II had ALMs like the Cyclone V
<ZirconiumX> Much like the Virtex 5 had LUT6s
<Clay_1> I am totally clueless when it comes to altera boards
<Clay_1> I used quartus for the first time last week
<Clay_1> and I cant really say I liked it
<Clay_1> what is your reason of prefering altera over xilinx?
<ZirconiumX> I use it from the command line so I don't have to bother with the GUI
<ZirconiumX> I first bought an FPGA for the MiSTer project, which uses the Terasic DE-10 Nano
<Clay_1> that's tcl, right ?
<ZirconiumX> Not necessarily
<Clay_1> you sound very knowledgeable on the subject :)
<ZirconiumX> Anyway, after getting immensely frustrated at Quartus, I looked for alternatives and stumbled upon Yosys
<ZirconiumX> And well, here I am
<Clay_1> That makes sense
<ZirconiumX> When you're reverse-engineering an FPGA you need to know the architecture as much as possible
<ZirconiumX> Or things don't make sense
<ZirconiumX> The ALM is a LUT6 like the Xilinx (CLB?)
<Clay_1> indeed
<ZirconiumX> But the internal architecture is very different
<Clay_1> xilinx has lut6 as part of a clb
<ZirconiumX> Xilinx LUT6s look like two LUT5s with separate outputs that get multiplexed by a sixth input
<ZirconiumX> So if you want to fit two LUT5s in a CLB they need to share all five terms
<ZirconiumX> Or else you can have small independent functions like a LUT2 and a LUT3 with no shared terms or two LUT3s with a shared term
<ZirconiumX> Altera ALMs look like four LUT4s which get multiplexed by two bits, but they have 8 inputs instead of 5+1
<Clay_1> "Xilinx LUT6s look like two LUT5s with separate outputs that get multiplexed by a sixth input" yes I would agree with that
<ZirconiumX> So you can implement two independent LUT4s in an ALM
<Clay_1> sounds more complex
<Clay_1> which are the logical lut inputs ?
<ZirconiumX> It depends on the function being implemented
<Clay_1> you can have a max of 6 inputs, right ?
<ZirconiumX> ...Kind of. You can implement *some* forms of a LUT7 in here
<Clay_1> wow
<ZirconiumX> Unfortunately you need specialised techmapping to take advantage of it
<Clay_1> do you have full controll over that or the tool will decide ?
<Clay_1> oh ok
<ZirconiumX> The synthesis tool handles it
<Clay_1> For Xilinx, I find the following paper very insightful of how luts work
<tpb> Title: Extract LUT Logics from a Downloaded Bitstream Data in FPGA - IEEE Conference Publication (at ieeexplore.ieee.org)
<Clay_1> you have access to ieeexplore, right ?
<ZirconiumX> I probably will at uni
<ZirconiumX> But it's a problem I've already solved
<Clay_1> the re of lut contents for quartus generated bitstreams ?
<ZirconiumX> Yeah
<Clay_1> cool
<Clay_1> how did you do that ?
* ZirconiumX sighs
<Clay_1> long story ?
<ZirconiumX> I need to write a paper about it so I don't have to keep explaining to everyone
<ZirconiumX> :P
<Clay_1> would be a good idea
<Clay_1> haha
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<ZirconiumX> For any boolean feature, you assign a unique non-zero identifier to it, and when you have all the ones enumerated, you produce a series of bitstreams where the Nth bitstream has the Nth bit of the feature index
<Clay_1> the design of that bitstream is a single lut ?
<ZirconiumX> "for any boolean feature"
<ZirconiumX> So not just LUTs
<ZirconiumX> For example, see the multiplexers feeding into the flip-flops?
<Clay_1> yes
<ZirconiumX> Those are boolean features that could be tested
<ZirconiumX> If you knew how to cause them
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<Clay_1> oh
<Clay_1> thats cool
<Clay_1> so you have done that for every such element ?
<ZirconiumX> At the moment no; I wanted to focus on routing, but that turns out to be a pain that requires thought
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<Adrofier> is anyone applying to gsoc this year?
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<Clay_1> ZirconiumX I see
<Clay_1> That's the part I would say that interests me the most in the xilinx part
<Clay_1> project x-ray seems to have solved this but I cant really understand their documentation :/ thus I came here to seek for help
<ZirconiumX> I mean, you can use the approach I mentioned for basically anything
<Clay_1> well, technically, routing is already documented in project xray, isnt it ?
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