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<ricos> I'd like to use nextpnr-xilinx with an artix7 and an ISERDESE2 (see https://pastebin.com/f8u1cCnP ). Unfortunately nextpnr-xilinx crashes with https://pastebin.com/xT4xPgDt . How could I get that working?
<tpb> Title: [VeriLog] `default_nettype none module top (input clk, output [7:0] LED_o, input pio3, - Pastebin.com (at pastebin.com)
<ZirconiumX> daveshah: ^
<daveshah> ricos: what Yosys version and script are you using?
<ricos> daveshah Yosys 0.9+932 (git sha1 342d91f, clang 9.0.0 -fPIC -Os)
<ricos> yosys -p "synth_xilinx -flatten -abc9 -nobram -arch xc7 -top top; write_json cmod.json" top.v
<ricos> I'm not exactly sure what you mean with "script". Is that just the command line or anything else?
<daveshah> Yes, the script is the bit in -p
<daveshah> I would recommend a newer Yosys. Older Yosys didn't do IO buffer insertion, and the IO buffer insertion in nextpnr isn't perfect
<daveshah> (can't immediately find where 342d91f comes from, but +932 is quite a bit older than +1706 I have here)
<ricos> ok, let me try ...
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<ricos> daveshah, somehow the sha1 is broken here, tried with Yosys 0.9+1706 (git sha1 342d91f, clang 9.0.1 -fPIC -Os)
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<ricos> daveshah, got E"RROR: JSON module whitebox attribute value is not a number" now
<daveshah> ricos: I think I pushed a fix for that to nextpnr-xilinx yesterday
<ricos> daveshah: with nextpnr-xilinx (6d80688) I now get terminate called after throwing an instance of 'std::invalid_argument'
<ricos> probably need to update prjxray ...
<daveshah> Depending on when you last built it, more important is probably just rebuilding the bba/bin
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<ricos> daveshah, it is still an issue but now https://pastebin.com/tN3STdQS
<tpb> Title: no dangling wires. checking net $auto$clkbufmap.cc:247:execute$278 driver: - Pastebin.com (at pastebin.com)
<daveshah> Might be an issue with the way you are using the ISERDES. Only a limited set of configs have been tested
<ricos> do you know which one where tested?
<tpb> Title: litedram/s7ddrphy.py at master · enjoy-digital/litedram · GitHub (at github.com)
<daveshah> Can you post your design somewhere? I can see if it would be possible to get it working with the current state of prjxray
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<ricos> daveshah, the design is here https://pastebin.com/f8u1cCnP not sure if it should work at all...
<tpb> Title: [VeriLog] `default_nettype none module top (input clk, output [7:0] LED_o, input pio3, - Pastebin.com (at pastebin.com)
<daveshah> IS_CLK_INVERTED("FALSE") should be (0)
<daveshah> (I need to work on a better error for this)
<daveshah> 7:1 mode hasn't been tested yet, I can't guarantee that it will work
<ricos> should the 0 used for all IS_* ?
<daveshah> Yes
<ricos> hence this worked :-)
<ricos> no crash, but it found no clocks
<daveshah> That's fine, it doesn't do timing analysis of SERDES atm
<ricos> ok
<ricos> daveshah, thanks for your help
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<Xiretza> daveshah: I know timing isn't very accurate yet, but I'm getting 20%+ higher fmax on :xilinx than on :router2, is that expected?
<daveshah> Yes, it's possible, router2 is optimised more for runtime than fmax at the moment
<daveshah> usually it's less than 10% different but an edge case is always possible
<Xiretza> ah, interesting
<daveshah> the inaccuracies in timing analysis might not be helping either
<daveshah> In the long run, when it has timing-driven rip up, router2 should also be able to give better timing (at the expense of runtime) for some trickier constraintsd
<Xiretza> nice, at the moment I don't have any timing concerns anyway, was just surprised to see such high numbers after updating everything
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