11:55 <sf-slack> <vermaakashraj> Hi everyone, I came across your project and would like to join and contribute. I can work with verilog, TCL, C++. And have basic understanding of creating verification environment with SystemVerilog. Let me know what can we work with. Thanks.

16:41 <hackerfoo> https://www.cnx-software.com/2020/02/18/antmicro-gem-asic-leverages-zglue-technology-to-quickly-bring-custom-arm-risc-v-socs-to-market/

18:18 <_whitenotifier-3> [prjxray] acomodi opened issue #1246: Instability of tilegrid for xc7z020 - https://git.io/Jv4Dm

18:21 <hackerfoo> Is there anything that needs reordered other than node ids and edge src and sinks? Just reversing the ids in the rr_graph leads to get_rr_node_index returning -1 because the size of `lookup` at rr_graph2.cpp:1289 is 0, so I think I'm missing something that affects the rr_node_indices.

18:22 <hackerfoo> Probably in `finish_rr_graph_rr_edges()` in rr_graph_uxsdcxx_serializer.h, but I don't see it yet.

18:25 <litghost> hackerfoo: That should be everything

18:26 <litghost> hackerfoo: It is worth noting that the stuff around PTC's is fairly fragile, so you may have exposed a latent bug

18:27 <hackerfoo> https://github.com/HackerFoo/Gorder/blob/master/Graph.cpp#L322-L332

18:27 <tpb> Title: Gorder/Graph.cpp at master · HackerFoo/Gorder · GitHub (at github.com)

18:27 <hackerfoo> litghost: That's what I'm afraid of.

18:28 <litghost> hackerfoo: The code is fragile, but it luckily fairly small

18:28 <litghost> hackerfoo: So I expect you should be able to identify and fix the bug

18:29 <hackerfoo> Yeah, in time.

21:58 <mithro> FYI -- https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/1151/files#diff-3 <-- Example SDC file used by the Titan benchmarks in VPR

21:58 <tpb> Title: Titan Benchmark SDC files by kmurray · Pull Request #1151 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com)

21:59 <mithro> It seems to have Set Input / Set Output Delay and set_clock_uncertainty