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<Xiretza> _florent_: do you know where you got the numbers for the ECP5 PLL VCO frequency range (https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/clock.py#L510)? they don't align with prjtrellis, but I can't find any source of truth (TN1263 doesn't mention it as far as I can tell).
<tpb> Title: litex/clock.py at master · enjoy-digital/litex · GitHub (at github.com)
<daveshah> Xiretza: the datasheet has them, iirc
<daveshah> The numbers in LiteX definitely don't look right, I also know from experimentation with Diamond that the range is 400-800MHz
<Xiretza> daveshah: oh, you're right, the ECP5 family datasheet has timing information, and f_vco is indeed 400-800 MHz.
<Xiretza> that's unfortunate, it means usb3_pipe needs at least two PLLs for its 100 -> (125, 200) clocks
<_florent_> Xiretza: thanks for the catching this, i'll update
<Xiretza> _florent_: I sent a PR
<_florent_> ah ok thanks!
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<_whitenotifier-3> [symbiflow-arch-defs] sjha2048 opened issue #1331: upgrading to ubuntu 18.04 - https://git.io/JvEzg
<_whitenotifier-3> [prjxray-dev-env] sjha2048 opened issue #1: upgrading to ubuntu 18.04 - https://git.io/JvEzr
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