space_zealot has quit [Ping timeout: 260 seconds]
freemint has quit [Quit: Leaving]
space_zealot has joined #symbiflow
citypw has joined #symbiflow
citypw has quit [Ping timeout: 240 seconds]
citypw has joined #symbiflow
space_zealot has quit [Ping timeout: 265 seconds]
Bertl_oO is now known as Bertl_zZ
citypw has quit [Ping timeout: 240 seconds]
citypw has joined #symbiflow
_whitelogger has joined #symbiflow
space_zealot has joined #symbiflow
citypw has quit [Ping timeout: 265 seconds]
citypw has joined #symbiflow
rvalles has quit [Ping timeout: 260 seconds]
rvalles has joined #symbiflow
citypw has quit [Ping timeout: 245 seconds]
citypw has joined #symbiflow
kraiskil has joined #symbiflow
kraiskil has quit [Ping timeout: 265 seconds]
kraiskil has joined #symbiflow
bunnie[m] has quit [*.net *.split]
tpb has quit [*.net *.split]
swetland has quit [*.net *.split]
ovf has quit [*.net *.split]
rvalles has quit [*.net *.split]
_florent_ has quit [*.net *.split]
bubble_buster has quit [*.net *.split]
abeljj[m] has quit [*.net *.split]
felix_ has quit [*.net *.split]
flokli has quit [*.net *.split]
ZipCPU has quit [*.net *.split]
stzsch has quit [*.net *.split]
proppy has quit [*.net *.split]
sorear has quit [*.net *.split]
somlo has quit [*.net *.split]
seraxis has quit [*.net *.split]
daveshah has quit [*.net *.split]
kgugala has quit [*.net *.split]
nickray has quit [*.net *.split]
sf-slack1 has quit [*.net *.split]
litghost has quit [*.net *.split]
xobs has quit [*.net *.split]
ZipCPU has joined #symbiflow
rvalles has joined #symbiflow
_florent_ has joined #symbiflow
flokli has joined #symbiflow
bubble_buster has joined #symbiflow
abeljj[m] has joined #symbiflow
felix_ has joined #symbiflow
bunnie[m] has joined #symbiflow
bjorkintosh has quit [*.net *.split]
Bertl_zZ has quit [*.net *.split]
bjorkintosh has joined #symbiflow
swetland has joined #symbiflow
tpb has joined #symbiflow
litghost has joined #symbiflow
proppy has joined #symbiflow
sorear has joined #symbiflow
stzsch has joined #symbiflow
seraxis has joined #symbiflow
kgugala has joined #symbiflow
somlo has joined #symbiflow
daveshah has joined #symbiflow
sf-slack1 has joined #symbiflow
nickray has joined #symbiflow
sf-slack has joined #symbiflow
sf-slack1 has quit [Write error: Broken pipe]
ovf has joined #symbiflow
diamondman has quit [Ping timeout: 260 seconds]
futarisIRCcloud has quit [Ping timeout: 260 seconds]
sorear has quit [Ping timeout: 244 seconds]
futarisIRCcloud has joined #symbiflow
sorear has joined #symbiflow
diamondman has joined #symbiflow
Bertl_zZ has joined #symbiflow
siriusfox has quit [Ping timeout: 268 seconds]
siriusfox has joined #symbiflow
<mithro> mkurc: For the changes to v2x - can you make sure they updated the documentation at https://python-symbiflow-v2x.readthedocs.io/en/latest/index.html?
<tpb> Title: Welcome to SymbiFlow Verilog to XML SymbiFlow Verilog to XML (V2X) 0.0-410-g4898bf6 documentation (at python-symbiflow-v2x.readthedocs.io)
<sf-slack> <mkurc> @mithro Ok, I'll update the docs.
citypw has quit [Ping timeout: 268 seconds]
<_whitenotifier-3> [prjxray] mithro opened issue #1219: 005-tilegrid failing on Zynq - https://git.io/JvGRL
<mithro> acomodi: It looks like the tilegrid fuzzer is failing on zynq? - https://github.com/SymbiFlow/prjxray/issues/1219
<tpb> Title: 005-tilegrid failing on Zynq · Issue #1219 · SymbiFlow/prjxray · GitHub (at github.com)
<sf-slack> <acomodi> @mithro: Hmm, this is unexpected, the question is why it is failing now? Is there a full log somewhere? I wonder whether this is related to the extra-part zynq010 or the zynq020
<mithro> acomodi: I put them in the github issue just then
<sf-slack> <acomodi> mithro: great, thanks
citypw has joined #symbiflow
<mithro> acomodi: Regarding the clock inversion
<tpb> Title: Merge pull request #935 from litghost/more_ilogic_bits · antmicro/prjxray@2d13b11 · GitHub (at github.com)
<mithro> acomodi: So IS_CLKB_INVERTED is never generated?
<mithro> `~/github/SymbiFlow/prjxray/database$ grep -R IS_CLKB_INVERTED` returns nothing...
<sf-slack> <acomodi> @mithro: exactly, as far as I have seen, by setting or unsetting the IS_CLKB_INVERTED, no bit is changing
<sf-slack> <acomodi> And, as a result, we lack the IS_CLKB_INVERTED feature
<mithro> acomodi: I think IS_CLKB_INVERTED is actually *implied* by the mode the serdes is being used in?
<tpb> Title: Re: IS_CLK_INVERTED attribute of ISERDES - Community Forums (at forums.xilinx.com)
<sf-slack> <acomodi> mithro: well, this tan explains the reason why we do not see any changes in the bits, I suppose. The problem now is, how to disable this implication? `MEMORY_QDR` interface type seems to be available only when using the MIG tool: https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf page 153
<mithro> acomodi: I think the inverter should be absorbed into the ISERDES primitive...
<mithro> Actually...
<mithro> Wait - how is the MCMM configured?
<sf-slack> <acomodi> You mean the PLL?
<mithro> Yeah
<mithro> acomodi: It's generating CLK and ~CLK right?
<sf-slack> <acomodi> No, it is generating a SYS_CLK, a SYS4x_CLK (fast clock for the IOSERDESes), a 90 degrees phased SYS4x_CLK
<tpb> Title: Snippet | IRCCloud (at www.irccloud.com)
<sf-slack> <acomodi> mithro: Could it be possible that, if this CLKB inverted is absorbed in the ISERDES primitive (and always active) we are feeding to the CLKB pin an inverted clock which is than inverted again by the pin inverter?
<tpb> Title: Snippet | IRCCloud (at www.irccloud.com)
<sf-slack> <acomodi> mithro: That bufg is necessary as, without it, the ~CLK would have been negated incorrectly without even passing through a BUFG
<mithro> acomodi: Did you modify the generated verilog at all?
<sf-slack> <acomodi> mithro: yes, but before that I have used Vivado to test it was correctly functioning. Apart from this we needed to add the OBUFs manually and the PLL phasing (90000 instead of 90)
<mithro> Can you provide the diff?
<sf-slack> <acomodi> Sure
<sf-slack> <acomodi> mithro: https://pastebin.com/hbbiPhhL
<tpb> Title: 23,24c23 < output ddram_reset_n, < output [3:0] led --- > output ddram_re - Pastebin.com (at pastebin.com)
<mithro> acomodi: Can you use unified diff output?
<sf-slack> <acomodi> mithro: here it is https://pastebin.com/mCWHStjf
<tpb> Title: --- ddr_uart.v 2020-02-04 13:26:04.860069367 +0100 +++ ../../../../prjxray/mini - Pastebin.com (at pastebin.com)
<mithro> acomodi: So the - lines are actually the ones you added?
<sf-slack> <acomodi> mithro: yes, @mkurc has dealt with the OBUF issues
<sf-slack> <acomodi> And this is applied also for the minilitex_ddr_test
<mithro> acomodi: This change doesn't look right
<mithro> acomodi: In the original source, the sys4x_clk signal was set up to drive CLK and CLKB but you changed CLKB to be ~sys4x_clk?
<sf-slack> <acomodi> Oh, actually I've sent you a wrong diff as I am currently changing the design to see whether, by leaving CLKB equal to CLK, things get to work. Anyway, the original source has CLKB equal to `~sys4x_clk` and CLK to `sys4x_clk`
<tpb> Title: litedram/s7ddrphy.py at 74f72f91a03156cfa23b7615dabd81c858d0b933 · enjoy-digital/litedram · GitHub (at github.com)
<sf-slack> <acomodi> mithro: yes, should be that one
<mithro> _florent_: You got a moment for a question about the clocking of the ISERDES in Artix-7 parts?
<sf-slack> <acomodi> mithro: this is the current correct diff in the uart-ddr PR: https://pastebin.com/9W4Ffe0q
<tpb> Title: --- ddr_uart.v 2020-02-04 13:52:01.455432878 +0100 +++ /home/alessandro/project - Pastebin.com (at pastebin.com)
<_florent_> mithro: yes
<mithro> _florent_: So in the ISERDES2 at https://github.com/enjoy-digital/litedram/blob/74f72f91a03156cfa23b7615dabd81c858d0b933/litedram/phy/s7ddrphy.py#L429-L430 you drive i_CLK with ddr_clk and i_CLKB with ~ddr_clk -- what is the expected outcome in Vivado?
<tpb> Title: litedram/s7ddrphy.py at 74f72f91a03156cfa23b7615dabd81c858d0b933 · enjoy-digital/litedram · GitHub (at github.com)
kraiskil has quit [Ping timeout: 260 seconds]
<mithro> mkurc: When writing the README.rst you should be describing the feature that is being tested rather than the bug itself
<sf-slack> <mkurc> @mithro: Right, I'll make them more focused on the feature.
<tpb> Title: dsp_combinational test SymbiFlow Verilog to XML (V2X) 0.0-410-g4898bf6 documentation (at python-symbiflow-v2x.readthedocs.io)
<_florent_> mithro: from UG471: "The high-speed secondary clock input (CLKB) is used to clock in the input serial data stream. In any mode other than MEMORY_QDR, connect CLKB to an inverted version of CLK."
<mithro> _florent_: Let me rephrase -- How do you expect the inverted ddr_clk be generated?
<mithro> _florent_: IE I would expect you would need to use the PLL to generate a 180 degree shifted ddr_clk ?
proteusguy has joined #symbiflow
<_florent_> mithro: i'm not sure since it's possible there is a hardware inverted directly in the ISERDESE2
<_florent_> mithro: on Ultrascale, i'm sure there is a hardware inverted on CLKB and you have parameter to specify the behaviour
<_florent_> mithro: i would need to look for 7-Series
kraiskil has joined #symbiflow
<_florent_> mithro: it also seems to be used like that on others designs:
<tpb> Title: fpga-family/lvds_iophy.v at 24d4df6d5ca62e078b4663cbdc7557ee0693f0e8 · LBL-BIDS/fpga-family · GitHub (at github.com)
<tpb> Title: AD9653_DAC3484/Frame_Check.v at 40df90dd0cc775e85fd6948b134ba87e29f5df59 · Blackieyan/AD9653_DAC3484 · GitHub (at github.com)
<mithro> This image seems to imply that the CLK / CLKB have inverters https://usercontent.irccloud-cdn.com/file/DEQ3mfci/image.png
space_zealot has quit [Ping timeout: 245 seconds]
kraiskil has quit [Ping timeout: 268 seconds]
kraiskil has joined #symbiflow
celadon has quit [Ping timeout: 265 seconds]
celadon has joined #symbiflow
<sf-slack> <acomodi> @mithro: I have tried to feed the same clock to both CLK and CLKB to ISERDESes, and the whole design passed through fasm2bels with no errors. There is no diff in the FASM files and, by inspecting the resulting .dcp, the CLKB inverter is enabled.
<sf-slack> <acomodi> Still, the design does not work on HW, I guess still for hold/setup violations
<mithro> acomodi: Okay, so Yosys should absorb the inverter into the ISERDES then I guess?
<mithro> acomodi: Does it work with Yosys->Vivado and FASM2BELs?
<sf-slack> <acomodi> mithro: Actually I am quite unsure of what happens there. By inspecting fasm2bels, the IS_CLKB_INVERTED parameter is added to the resulting verilog. I am not sure this is a Yosys doing. This inverter seems to be working in a pretty strange way. By setting or unsetting in the verilog instantiation, nothing changes)
<sf-slack> <acomodi> mithro: I need to check that
space_zealot has joined #symbiflow
citypw has quit [Ping timeout: 248 seconds]
space_zealot has quit [Ping timeout: 268 seconds]
space_zealot has joined #symbiflow
proteus-guy has joined #symbiflow
space_zealot has quit [Remote host closed the connection]
space_zealot has joined #symbiflow
az0re has joined #symbiflow
space_zealot has quit [Remote host closed the connection]
space_zealot has joined #symbiflow
kraiskil has quit [Ping timeout: 268 seconds]
bunnie[m] has quit [*.net *.split]
sf-slack has quit [*.net *.split]
rvalles has quit [*.net *.split]
_florent_ has quit [*.net *.split]
bubble_buster has quit [*.net *.split]
abeljj[m] has quit [*.net *.split]
felix_ has quit [*.net *.split]
flokli has quit [*.net *.split]
ZipCPU has quit [*.net *.split]
bunnie[m] has joined #symbiflow
sf-slack has joined #symbiflow
abeljj[m] has joined #symbiflow
bubble_buster has joined #symbiflow
ZipCPU has joined #symbiflow
felix_ has joined #symbiflow
rvalles has joined #symbiflow
flokli has joined #symbiflow
_florent_ has joined #symbiflow
<Xiretza> daveshah: route failure from SITEWIRE/SLICE_X7Y94/C6LUT_O6 to SITEWIRE/SLICE_X2Y97/CEUSEDMUX_OUT with f49d299, I can give you the json and xdc in a sec
<daveshah> Thanks, I will look tomorrow. I think this is probably another shift register issue
<Xiretza> daveshah: oh, somehow my -nosrl got lost, will retry with that
space_zealot has quit [Ping timeout: 240 seconds]
<Xiretza> yep, seems like it, router starts fine with -nosrl. anyway, here's the files: https://misc.xiretza.xyz/repro/f49d299b_route_fail.tar.gz
<daveshah> Thanks!
space_zealot has joined #symbiflow
<Xiretza> huh, another interesting problem: just updated yosys (I'm assuming that's what's the problem), now router2 is stuck at overused=147 and it's not going down any further.
<litghost> Xirertza: What part are you targetting?
<Xiretza> litghost: xc7a35tcsg324
<Xiretza> it worked a moment ago and the only thing that changed is yosys, I'll downgrade that and try again
kraiskil has joined #symbiflow
bjorkintosh has quit [Quit: Leaving]
<Xiretza> yeah, that's it, specifically 34d2fbd2 "Add opt_lut_ins pass". I'll hop on over to #yosys then
kraiskil has quit [Ping timeout: 265 seconds]
bjorkintosh has joined #symbiflow
kraiskil has joined #symbiflow
bjorkintosh has quit [Quit: Leaving]
space_zealot has quit [Ping timeout: 260 seconds]
kraiskil has quit [Ping timeout: 240 seconds]
tpb has quit [Remote host closed the connection]
tpb has joined #symbiflow