<tpb>
Title: Welcome to SymbiFlow Verilog to XML SymbiFlow Verilog to XML (V2X) 0.0-410-g4898bf6 documentation (at python-symbiflow-v2x.readthedocs.io)
<sf-slack>
<mkurc> @mithro Ok, I'll update the docs.
citypw has quit [Ping timeout: 268 seconds]
<_whitenotifier-3>
[prjxray] mithro opened issue #1219: 005-tilegrid failing on Zynq - https://git.io/JvGRL
<sf-slack>
<acomodi> @mithro: Hmm, this is unexpected, the question is why it is failing now? Is there a full log somewhere? I wonder whether this is related to the extra-part zynq010 or the zynq020
<mithro>
acomodi: I put them in the github issue just then
<tpb>
Title: Re: IS_CLK_INVERTED attribute of ISERDES - Community Forums (at forums.xilinx.com)
<sf-slack>
<acomodi> mithro: well, this tan explains the reason why we do not see any changes in the bits, I suppose. The problem now is, how to disable this implication? `MEMORY_QDR` interface type seems to be available only when using the MIG tool: https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf page 153
<sf-slack>
<acomodi> mithro: Could it be possible that, if this CLKB inverted is absorbed in the ISERDES primitive (and always active) we are feeding to the CLKB pin an inverted clock which is than inverted again by the pin inverter?
<sf-slack>
<acomodi> mithro: That bufg is necessary as, without it, the ~CLK would have been negated incorrectly without even passing through a BUFG
<mithro>
acomodi: Did you modify the generated verilog at all?
<sf-slack>
<acomodi> mithro: yes, but before that I have used Vivado to test it was correctly functioning. Apart from this we needed to add the OBUFs manually and the PLL phasing (90000 instead of 90)
<mithro>
acomodi: So the - lines are actually the ones you added?
<sf-slack>
<acomodi> mithro: yes, @mkurc has dealt with the OBUF issues
<sf-slack>
<acomodi> And this is applied also for the minilitex_ddr_test
<mithro>
acomodi: This change doesn't look right
<mithro>
acomodi: In the original source, the sys4x_clk signal was set up to drive CLK and CLKB but you changed CLKB to be ~sys4x_clk?
<sf-slack>
<acomodi> Oh, actually I've sent you a wrong diff as I am currently changing the design to see whether, by leaving CLKB equal to CLK, things get to work. Anyway, the original source has CLKB equal to `~sys4x_clk` and CLK to `sys4x_clk`
<tpb>
Title: dsp_combinational test SymbiFlow Verilog to XML (V2X) 0.0-410-g4898bf6 documentation (at python-symbiflow-v2x.readthedocs.io)
<_florent_>
mithro: from UG471: "The high-speed secondary clock input (CLKB) is used to clock in the input serial data stream. In any mode other than MEMORY_QDR, connect CLKB to an inverted version of CLK."
<mithro>
_florent_: Let me rephrase -- How do you expect the inverted ddr_clk be generated?
<mithro>
_florent_: IE I would expect you would need to use the PLL to generate a 180 degree shifted ddr_clk ?
proteusguy has joined #symbiflow
<_florent_>
mithro: i'm not sure since it's possible there is a hardware inverted directly in the ISERDESE2
<_florent_>
mithro: on Ultrascale, i'm sure there is a hardware inverted on CLKB and you have parameter to specify the behaviour
<_florent_>
mithro: i would need to look for 7-Series
kraiskil has joined #symbiflow
<_florent_>
mithro: it also seems to be used like that on others designs:
<sf-slack>
<acomodi> @mithro: I have tried to feed the same clock to both CLK and CLKB to ISERDESes, and the whole design passed through fasm2bels with no errors. There is no diff in the FASM files and, by inspecting the resulting .dcp, the CLKB inverter is enabled.
<sf-slack>
<acomodi> Still, the design does not work on HW, I guess still for hold/setup violations
<mithro>
acomodi: Okay, so Yosys should absorb the inverter into the ISERDES then I guess?
<mithro>
acomodi: Does it work with Yosys->Vivado and FASM2BELs?
<sf-slack>
<acomodi> mithro: Actually I am quite unsure of what happens there. By inspecting fasm2bels, the IS_CLKB_INVERTED parameter is added to the resulting verilog. I am not sure this is a Yosys doing. This inverter seems to be working in a pretty strange way. By setting or unsetting in the verilog instantiation, nothing changes)
<sf-slack>
<acomodi> mithro: I need to check that
space_zealot has joined #symbiflow
citypw has quit [Ping timeout: 248 seconds]
space_zealot has quit [Ping timeout: 268 seconds]
space_zealot has joined #symbiflow
proteus-guy has joined #symbiflow
space_zealot has quit [Remote host closed the connection]
space_zealot has joined #symbiflow
az0re has joined #symbiflow
space_zealot has quit [Remote host closed the connection]
space_zealot has joined #symbiflow
kraiskil has quit [Ping timeout: 268 seconds]
bunnie[m] has quit [*.net *.split]
sf-slack has quit [*.net *.split]
rvalles has quit [*.net *.split]
_florent_ has quit [*.net *.split]
bubble_buster has quit [*.net *.split]
abeljj[m] has quit [*.net *.split]
felix_ has quit [*.net *.split]
flokli has quit [*.net *.split]
ZipCPU has quit [*.net *.split]
bunnie[m] has joined #symbiflow
sf-slack has joined #symbiflow
abeljj[m] has joined #symbiflow
bubble_buster has joined #symbiflow
ZipCPU has joined #symbiflow
felix_ has joined #symbiflow
rvalles has joined #symbiflow
flokli has joined #symbiflow
_florent_ has joined #symbiflow
<Xiretza>
daveshah: route failure from SITEWIRE/SLICE_X7Y94/C6LUT_O6 to SITEWIRE/SLICE_X2Y97/CEUSEDMUX_OUT with f49d299, I can give you the json and xdc in a sec
<daveshah>
Thanks, I will look tomorrow. I think this is probably another shift register issue
<Xiretza>
daveshah: oh, somehow my -nosrl got lost, will retry with that
<Xiretza>
huh, another interesting problem: just updated yosys (I'm assuming that's what's the problem), now router2 is stuck at overused=147 and it's not going down any further.
<litghost>
Xirertza: What part are you targetting?
<Xiretza>
litghost: xc7a35tcsg324
<Xiretza>
it worked a moment ago and the only thing that changed is yosys, I'll downgrade that and try again
kraiskil has joined #symbiflow
bjorkintosh has quit [Quit: Leaving]
<Xiretza>
yeah, that's it, specifically 34d2fbd2 "Add opt_lut_ins pass". I'll hop on over to #yosys then