06:03 <mithro> litghost: New database push at https://github.com/mithro/prjxray-db/compare/SymbiFlow:master...master

06:03 <tpb> Title: Comparing SymbiFlow:master...mithro:master · SymbiFlow/prjxray-db · GitHub (at github.com)

10:39 <jayanthj737> Hello Sir, Really Interested and looking forward towards working on Open Source PROJECT handles by Symbiflow. I would be pleased to know more about it and also to gather enough skills for the sameThanking You.Jayanth Jayadevan

11:31 <ZirconiumX> jayanthj737: have you ever used Verilog?

11:32 <ZirconiumX> I'm not mithro, but I can offer some ideas of my own

11:36 <jayanthj737> No thats my only concern. But have programmed PIC ICs

11:36 <ZirconiumX> (for the record I am not a sir)

11:37 <ZirconiumX> Right. You don't *need* to know Verilog but if you're going to apply for Symbiflow you should read up on FPGA architecture.

11:37 <ZirconiumX> PICs are nowhere close to FPGAs; the programming model is fundamentally different

11:42 <ZirconiumX> jayanthj737: ^

11:44 <jayanthj737> Sure thing.

11:45 <ZirconiumX> The talk "Everything Wrong With FPGAs" by Ben Widawsky gives a good overview of FPGA architecture, even if they're not the main focus of the talk

11:46 <ZirconiumX> It's also not *that* long

11:50 <ZirconiumX> jayanthj737: a personal idea for GSoC I've had is in how Yosys maps to FPGA LUTs

12:06 <abeljj[m]> a personal idea for GSoC I've had is in how Yosys maps to FPGA LUTs

12:06 <abeljj[m]> ZirconiumX , isn't yosys a synthesis suite for vlsi?

12:08 <ZirconiumX> It *can* target VLSI, but much of the present work goes into FPGAs as a back-end

12:08 <ZirconiumX> Lattice iCE40 and ECP5 FPGAs both have mature synthesis targets, abeljj[m]

12:09 <ZirconiumX> Xilinx work is progressing, although I'm unfamiliar with the place-and-route side of things

12:12 <ZirconiumX> And I've been trying to target Intel chips

12:15 <abeljj[m]> I have used yosys with qflow, where the target technology were openly available. But with fpga and intel chips is it a try and error method?

12:16 <ZirconiumX> You're going to have to be more specific: there is no trial-and-error needed for synthesis

12:17 <abeljj[m]> Since the architecture is closed, how is synthesis done?

12:17 <ZirconiumX> Either the FPGA bitstream gets reversed or you can use Quartus to perform place-and-route

12:18 <ZirconiumX> The first two are how iCE40 and ECP5 work, the latter is my current target, and what Xilinx can do too

12:18 <ZirconiumX> (but for Vivado/ISE)

15:10 <yusef> "Support Xilinx XC9500XL CPLD series" so, what do we have to do in this?

15:14 <ZirconiumX> yusef: reverse engineer the bitstream format, mostly.

15:23 <ZirconiumX> Which requires using ISE and that won't be very fun :P

16:31 <mithro> Did we ever write that RAM in bitstream patching for Xilinx Series 7?

16:31 <sf-slack> <kgugala> I don't think so

22:38 <Jihad> Hello everybody, what is the topics should I study?