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<_whitenotifier-3> [yosys] rakeshm75 opened issue #65: Branch: Quicklogic : Multiplier primitive instance should be qlal4s3_mult_cell_macro - https://git.io/JvDbe
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<clay_1> Good morning people
<clay_1> is there any formal way to cite symbiflow and xray ?
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<KaBoom25> Hi
<KaBoom25> Anyone active?
<clay_1> hey
<KaBoom25> First time here...
<clay_1> wellcome :)
<KaBoom25> Anyone into ASIC?
<clay_1> I believe it is out of scope here but I am very new myself so dont take my word for it
<KaBoom25> Oh
<KaBoom25> I was asking because, I am looking for an open source synthesis tool
<KaBoom25> Any ideas?
<clay_1> Sorry I dont
<sf-slack> <eddy.gta17> You may use qflow at opencircuitdesign.com
<sf-slack> <eddy.gta17> Also there was the asicone, but you may have to contact the owners to access it.
<sf-slack> <eddy.gta17> Then the DARPA sponsored openROAD project.
<sf-slack> <eddy.gta17> It is FPGA that has fewer open source tools.
<KaBoom25> I can agree to that
<KaBoom25> Thanks foe=r the suggestions
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<_whitenotifier-3> [ideas] drom opened issue #43: Streaming VCD parser - https://git.io/JvyCy
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<_whitenotifier-3> [ideas] drom opened issue #44: SystemVerilog parser using Tree-Sitter - https://git.io/JvyCb
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