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<lambda>
litghost: I'm using an xc7a35t, which seems to have two CMT_TOP_L_UPPER_T PLLs in the bottom right, and three CMT_TOP_R_UPPER_T PLLs along the left side of the chip
<lambda>
(at least that's what the Vivado device view suggests)
<lambda>
mithro: I can try vpr. the design is open source at https://gitlab.com/YARM-project/soc/, but it's VHDL - but I expect just dumping it to a verilog netlist with yosys should work?
<sf-slack>
<mithro> This content can't be displayed.
<tpb>
Title: Sign in · GitLab (at gitlab.com)
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<CMP1>
Hey everyone. I would like some help regarding the term of Slice. As I can see typically a Tile has two of them. In the case of CLB there are sliceL and sliceM slices. But what about DSPs and BRAMs?
<CMP1>
are their tiles considered to have slices ?
<sf-slack>
<acomodi> SLICE is a `Site` within only the CLB tiles
<sf-slack>
<acomodi> Tiles can have sites
<CMP1>
So CLBs, BRaMs and DSPs have two sites each
<CMP1>
actually thats falso BRAms have more sites
<sf-slack>
<acomodi> Each tile can have its own specific set of sites, it doesn't need to be 2
<CMP1>
and also the interconnect box inside CLBs are a site as well, right ?
<CMP1>
I see, so every "box" inside a tile is a site
<sf-slack>
<acomodi> For the 7series the CLB has 2 sites, which are the two Slices you mentioned
<CMP1>
oh so the fake pip box they have is not considered a site ?
<sf-slack>
<acomodi> Exactly, that's not a site
<CMP1>
so slices are called only the CLB sites ?
<CMP1>
I mean that used to be my earlier understanding but then I saw the title of ug479 beeing `7 Series DSP48E1 Slice`
<CMP1>
and that started to make me believe that more tiles have divisions called slices or something
<sf-slack>
<eddy.gta17> Does project icestorm support system verilog? I am trying to synthesise the ibex core for the ice40. Yosys gives errors on the .sv file and the .v file that was converted using sv2v. I read this is due to the parser in yosys. Is there a workaround?
<sf-slack>
<acomodi> CMP1: so, to answer your questions, you can see in the device view on Vivado, that when you select a tile it opens the `Tile properties`, when you navigate within that tile you can select the sites, which will open the `Site properties` . The naming is a convention. CLB have two SLICE sites, DSP have two DSP48E1 sites, BRAMs have 2 RAMB18E1 and 1 RAMB36E1 sites and so on
<sf-slack>
<acomodi> @eddy.gta17 I am not sure whether the synthesis pass for the ice40 will pass, but here there are ibex core .v files that has been translated from .sv and can be correctly synthesized for the artix7
<CMP1>
I see, now things are more clear. In my uneducated view the term slice seems redundant and can cause only confusion since siteL and site
<CMP1>
siteM would work to describe everything, right ?
<sf-slack>
<acomodi> CMP1: what do you mena by describe everything?
<CMP1>
I mean by removing the term slice we would still be able to address every unit with the term site
<sf-slack>
<eddy.gta17> @acomodi I will try the .v files in the Symbiflow repo. Are they the same as the lowRISC or any keywords changed?
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<sf-slack>
<acomodi> @eddy.gta17 They are the same. Only difference is in the absence of the clock gating part.
<sf-slack>
<acomodi> CMP1: I believe I am not completely following. What do you mean by unit, and from where would you remove the term slice?
<sf-slack>
<acomodi> CMP1: one more thing is that, if you see in the documentation something like `DSP SLICE` it should actually refer not to the sites, but the DSP tile itself.
<CMP1>
I meant that since all slices are sties but not all sites slices, by introducing different types of sites (like siteL, siteM) we wouldnt need the term slice.
<CMP1>
Hmm but the title was `7 Series DSP48E1 Slice` and as you said erlier, DSP48E1 is a site of a DSP tile
<sf-slack>
<acomodi> But the fact is that with `siteL` and `siteM` there would be a lot of confusion. The term `SLICE` within the CLB clearly eliminates any doubts. CLBs are formed by sites named `SLICEs`
<sf-slack>
<acomodi> As I said `7 Series DSP48E1 Slice` refers to the DSP "Tile". In this case the term Slice has nothing to do with the CLB Slices
<CMP1>
I agree with that but it seems the term slice is not only used there--> hence the confusion
<CMP1>
But at least i think I have them clear in my head now. Thank you very much !
<sf-slack>
<acomodi> No problem ;)
<CMP1>
:D
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<CMP1>
Hmm what about the relationship between configuration packets and configuration frames ? Configuration packets contain a number of configuration frames depending on their type ?
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<sf-slack>
<tmichalak> configuration packages consist of header and payload, Type 1 Configuration packets have a register address field so you can write a configuration frames' address to the FAR register followed by a Type 2 configuration packet writes to the FDRI register with all the words within that configuration frame
<CMP1>
So for a type one packet, the header will idicate that it is type 1 and the payload will be one configuration frame's address ?
<sf-slack>
<tmichalak> In brief the configuration frame address has to be written to the FAR (Frame Address Register) register and the configuration words to the FDRI (Frame Data Register Input) register)
<sf-slack>
<tmichalak> And to do this you need a combination of Type1 and Type2 packets
<CMP1>
In the way I understand it from the ug, type 2 will only be used if the word count supported by type 1 is not sufficient
<CMP1>
but I don't understand what this word count depends on
<sf-slack>
<tmichalak> Yes, so you can configure a number of frames using the Type1 packets only
<CMP1>
does it try to write all the configuration frames at once ? so for small designs a type1 only is sufficient but for bigger ones you need type 2 as well ?
<litghost>
lambda: Both CMT_TOP_L_UPPER_T and CMT_TOP_R_UPPER_T have tilegrid base addresses, so both should work. I expect that the the problem is in how nextpnr-xilinx is emitting the FASM, not in the database
<sf-slack>
<tmichalak> CMP1: It doesn't really depend on the design size. You can write 20 configuration frames with 10 Type1 writes (20 * 101 < 2048) or just with one Type2
<lambda>
litghost: oh, nice! I'll look into that then if daveshah isn't already on it
<_whitenotifier-3>
[prjtrellis] minecraft2048 opened issue #131: I think multiplier inference is working in prjtrellis and yosys master - https://git.io/JvHwk
<sf-slack>
<tmichalak> CMP1: Since Type1 one can write 2048 words at once
<CMP1>
tmichalak but wont this normally happen automatically by vivado ?
<daveshah>
lambda: feel free to have a go, I think something probably just needs renaming
<daveshah>
Most likely an L and R swapped in the output or similar
<lambda>
alright, will do
<sf-slack>
<tmichalak> CMP1: Depends on you bootgen setting, if you have PER_FRAME_CRC enabled then no
<CMP1>
oh I think I understand now why you said that the design size doesnt matter. No matter how big or small the device is, all frames will be read (even the empty ones) so the number of words that have to be read are FPGA device specific ?
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<sf-slack>
<tmichalak> CMP1: Yes, it's more FPGA family dependent, but for Series7 it's always 101 words
<CMP1>
oh yes, but I didnt mean that, I meant the number of 101 32-bit words that need to be read in total
<sf-slack>
<tmichalak> The number of words in a frame is constant for Series7 it's 101 32-bit words
<CMP1>
and how about the number of frames in a device, isnt that device constant depending on how bi it is or something like that ?
<CMP1>
big *
<sf-slack>
<tmichalak> frame addressing is described in SymbiFlow's documentation and also in the Configuration Guide, the number of frames really depends on the size of the FPGA
<CMP1>
Nice, and in every configuration all frames are read regardless if they are empty or not, right ?
<sf-slack>
<tmichalak> right
<CMP1>
great, thanks :)
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<CMP1>
Has CFG_CLB been found in any bit stream up to now ?
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<lambda>
daveshah litghost: fasm2frames.py is saying `Segment DB CMT_TOP_R_LOWER_B, key CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS0.MMCM_CLK_FREQ_BB_REBUF0_NS not found from line 'CMT_TOP_R_LOWER_B_X8Y61.MMCM_CLK_FREQ_BB_NS0.MMCM_CLK_FREQ_BB_REBUF0_NS'`.
<lambda>
I'm assuming that's a pip connecting MMCM_CLK_FREQ_BB_REBUF0_NS and MMCM_CLK_FREQ_BB_NS0 in a CMT_TOP_R_LOWER_B - but I see that exact pip ("CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_REBUF0_NS<<->>MMCM_CLK_FREQ_BB_NS0") in tile_type_CMT_TOP_R_LOWER_B.json.
<litghost>
That's a MMCM pip?
<litghost>
We do *not* have fuzzing for the MMCM part of the CMT interconnect
<litghost>
Not sure why nextpnr is going down there though
<lambda>
ohh, so this might not be directly related to enabling more PLLs in nextpnr, but rather to the fact that litedram now gets through PNR - it of course uses PHASERs and such, maybe those just aren't supported enough yet
<litghost>
I don't think LiteDRAM used PHASERs? And yes, PHASERs are not currently supported
<lambda>
I also get two errors from PIPs in CMT_TOP_R_UPPER_B_X8Y31, which looks to be a PHASER
<daveshah>
It seems like nextpnr is just using pips that it shouldn't
<daveshah>
Is this the same netlist as before, I can have a look tomorrow
<daveshah>
I think I've seen this phaser pip issue before
<lambda>
daveshah: I'll retry with the old netlist real quick, should be the same though yes
<litghost>
lambda: It is worth noting that I expect the fuzzers written for the PLL will work with the MMCM with a "s/PLL/MMCM/", but it hasn't been tried yet
<FFY00>
the thing is that in python you should still keep track of breaking changes
<mithro>
FFY00: Yeah, we are slowly moving towards using more type hints
<mithro>
FFY00: But it is pretty easy to make breaking changes in Python without knowing it
<mithro>
FFY00: "If you want it to work, you should put a test on it" :-)
<FFY00>
but semver probably is too aggressive (at least for your development environment) as it would probably require a major version bump every release
<FFY00>
mithro, exactly
<FFY00>
if a certain part of your code does not have tests, it as good as broken
<FFY00>
because changes are it will eventually break
<FFY00>
*chances
<mithro>
There was a quote I found the other day which went something like "Everyone has a testing environment, some people are just lucky enough for it to be seperate from their production environment"
<mithro>
FFY00: With low test coverage and dynamic language like python you want your users to try and run with your changes ASAP so they can report bugs / breaking issues as quickly as they can so you can fix them before they affect a lot of people
<FFY00>
I don't think it correctly detect any license with a custom copyrighted field?