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<_whitenotifier-3>
[sv-tests] hzeller opened issue #676: Kokoro tests not always succeed recently - https://git.io/JvwJI
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<_whitenotifier-3>
[prjxray-bram-patch] kgugala opened issue #10: Setup CI - https://git.io/JvwYm
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<clay_1>
Hey hey people !
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<_whitenotifier-3>
[yosys] kkumar23 opened issue #60: Branch : quicklogic : Issue while loading the edf file on spde "$_dlatch_p_.edi' " - https://git.io/Jvw8T
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<clay_1>
I cloned symbiflow and tried to run the fasm2bels
<clay_1>
So far I tried running python3 fasm2bels.py
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<clay_1>
but this got me errors
<clay_1>
In the read me I saw that the correct format is python3 -mfasm2bels <options> <verilog> <tcl>
<clay_1>
so <verilog> and <tcl> should be the specified by me outut files
<clay_1>
and options should be - `--connection_database` , `--db_root`, `--part` ,'fasm_file` separated by space ?
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<litghost>
Yes?
<clay_1>
so I should write something like python3 -mfasm2bels /x1 /x2 xc7a35tcpg236-1 file.fasm file.v file.xdc ?
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<_whitenotifier-3>
[conda-packages] acomodi opened issue #79: Yosys package cannot be found - https://git.io/Jvw28
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<lambda>
getting a prjxray.fasm_assembler.FasmInconsistentBits exception from fasm2frames.py on nextpnr-xilinx output - specifically, LIOB33_X0Y137.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 and LIOB33_X0Y137.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY are colliding.
<lambda>
which is weird, since the port that's bound to that site is a button input used as a clock, definitely not an output
<daveshah>
Sounds like something is broken in nextpnr I'll have a look but it would be tomorrow
<lambda>
daveshah: I just realized what's going on - I didn't have all my ports in the .xdc, so nextpnr decided to put an output on the same site as my clock input. constrained all my ports, now everything works
<daveshah>
Ah that makes sense, it's probably something odd like double counting IO sites due to the different modes
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