<litghost>
clay_1: You are using fasm2bels in a weird way. fasm2bels is designed to convert the input FASM file into a top level verilog file that matches the original so that testbenches can run on the post-place&route output
<litghost>
clay_1: Some of the arguments to fasm2bels were specifically for the original bitstream, before you replaced it
<litghost>
clay_1: Solution is to invoke fasm2bels without arguments specific to the original design
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<sf-slack>
<aryap> hello
<sf-slack>
<aryap> is the symbiflow fork of vtr significantly different to upstream, currently?
<litghost>
aryap: Yes
<sf-slack>
<aryap> looks like there was a sync only a few days ago
<sf-slack>
<aryap> ok
<litghost>
aryap: We periodically bring in upstream changes, but there are significant downstream changes required for the flow
<sf-slack>
<aryap> is this mostly plumbing or significant work on QoR?
<sf-slack>
<aryap> i guess i can just run both
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<sf-slack>
<aryap> thanks :pray:
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<hackerfoo>
aryap: Upstream VtR won't work with symbiflow-arch-defs. We are working to upstream our changes, but it takes time.
<mithro>
aryap: litghost has been working hard to get a bunch of stuff upstream lately
<sf-slack>
<aryap> nice work :clap:
<sf-slack>
<aryap> should i be able to run any of the titan benchmarks on the xc7a50t arch from symbiflow-arch-defs?
<sf-slack>
<aryap> i get this a lot: ```Error 1: [blah]/symbiflow-vtr/libs/libvtrutil/src/vtr_util.cpp:190 Failed to convert string '{iopath_A1_O5}' to float```
<mithro>
aryap: That means you have broken the symbiflow architecture generation -- it hasn't patched in the timing information
<mithro>
aryap: Nobody has gotten the titan benchmarks (**not** to be confused with a benchmark containing opentitan) running on symbiflow architectures -- but that would be an excellent project
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<HEGAZY>
Hi all, again, remember me?
<HEGAZY>
so we talked yesterday about the Gsoc project for #symbiflow , I've thought it through and I am intersted in "system verilog feature detector" you told me about,
<HEGAZY>
I have an initial plan on how the work is going to go, but first i have couple of questions I need to discuss with you :D
<HEGAZY>
mithro said "For example, we would love to work on a "system verilog feature detector" which is able to give you a list of the system verilog functionality a project is using and thus which tools will are more likely to be compatible with the project"
<HEGAZY>
- I see that the third party tools takes .sv files directly, so are the tools already support some kinda of verilog structure format that i should return as a result? or is this for future integration?
<HEGAZY>
- why not use an existing parser for sv, I mean all the third party tools like yosys parse the code 1st and their parser opensource that can be ported here right?
<ZirconiumX>
HEGAZY: essentially "because nobody's done it yet".
<ZirconiumX>
VHDL support is more or less third-party