<_whitenotifier-3>
[prjxray] mithro opened issue #1286: Instability in DSP timing fuzzer - https://git.io/Jv5JV
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<daniellimws>
Working on a project using one of Xilinx's IP cores, is there a way in prjxray to run simulations on that core? Or I have no choice but to use Vivado's simulator
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<litghost>
Most hardblocks are missing simulation models right now
<litghost>
Adding simulation models is an open task
<daniellimws>
I suppose that it would take some effort to do that for each core?
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<litghost>
Not core, hardblock
<litghost>
So DSP, BRAM, PHASER_IN/OUT, PCIE
<daniellimws>
Oh in the case of the CORDIC IP that I am using now, it uses the PHASER_* block am I right?
<daniellimws>
So once a simulation model is built for the PHASER_IN/OUT hardblock, it is possible to simulate the CORDIC ips? Am I understanding this correctly?
<litghost>
Before that, we need to fuzz PHASER_IN/_OUT, which hasn't been done yet
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<_whitenotifier-3>
[yosys] rakeshm75 opened issue #66: Branch: Quicklogic : Functional issue in the design - https://git.io/Jv5GK
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<sf-slack>
<r.jordans> Hi all, does anyone know what the current status of the soft-error-detection block for ECP5 is? I see that there is a SEDGA test in the fuzzers directory but I don't see anything yet in the database
<daveshah>
r.jordans: It isn't currently supported
<sf-slack>
<r.jordans> Anything I can do to get it supported?
<daveshah>
the main blocker is reverse engineering the CRC32 (in particular what exactly it is calculated over) inserted in the bitstream in SED mode
<daveshah>
the nextpnr changes to support the SED primitives are simpler and I am happy to do those once the CRC is sorted
<sf-slack>
<r.jordans> ok, so I guess that's the crc of the bitfile it compares against in the hardware? I guess that it's mainly the polynome that's missing? do we already have a way of getting some example crcs for different bitfiles?
<daveshah>
No, setting up something up to do that would be a first step
<sf-slack>
<r.jordans> ah, ok
<sf-slack>
<r.jordans> I don't have much experience with this but would like to see this working so I'll try to free up some time
<sf-slack>
<r.jordans> I did however do a bit of reverse engineering crc in the past though so hopefully that can help here
<FFY00>
daveshah, what work has been done reverse engineering the crc?
<daveshah>
The normal CRC16 is fully RE'd its the BUYPASS algorithm
<daveshah>
I haven't looked at the SED CRC32 at all, but based on the CRC16 it's probably a standard algorithm
<FFY00>
do you have samples?
<daveshah>
The hard part is probably working out what it is calculated over (and in what order) rather than the polynomial it uses
<daveshah>
No
<FFY00>
yes, there aren't many well suited polynomials
<FFY00>
well, if it is following the standard that shouldn't be an issue
<daveshah>
What standard?
<FFY00>
the issue if finding the xor in, xor out, reflect in and reflect out
<FFY00>
crc32
<daveshah>
ah
<FFY00>
32 bits is a bit, but it could be bruteforced with some cleaver techniques
<FFY00>
since crc is not really designed to be a protection mechanism
<FFY00>
I was looking into this a few days ago
<FFY00>
to reverse engineer the crc of a firmware I wanted to replace