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<sf-slack>
<kgugala> hi @ahegazy do you have any particular PR in mind?
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<clay_1>
Good morning !
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<HEGAZY>
@kgugala sv-tests #687
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<sf-slack>
<kgugala> @HEGAZY somebody will review the PR this week (probably next 2 days)
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<n45405>
hey @kgugala sv-tests #687
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<clay_1>
While trying to run the fasm2pips I run into the following errors
<clay_1>
`./utils/fasm2pips.py --part xc7a35tcpg236-1 1.fasm`Traceback (most recent call last): File "./utils/fasm2pips.py", line 50, in <module> main() File "./utils/fasm2pips.py", line 46, in main ' '.join('[get_pips {}]'.format(pip) for pip in inner()))) File "./utils/fasm2pips.py", line 46, in <genexpr> ' '.join('[get_pips {}]'.format(pip)
<clay_1>
for pip in inner()))) File "./utils/fasm2pips.py", line 41, in inner if pip.net_from == parts[2] and pip.net_to == parts[1]:IndexError: list index out of range
<clay_1>
Could it be because my part.yaml location is not set correctly ? ( since in similar issue I had with xc7frames2bit i had to use the `part_file` argument ?
<sf-slack>
<kgugala> @clay_1 are you able to provide the fasm file you're trying to run through the tool?
<clay_1>
here ? sure
<clay_1>
its a fasm file created from the bit2fasm.py
<tpb>
Title: Easyupload.io - Upload files for free and transfer big files easily. (at easyupload.io)
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<litghost>
clay_1: fasm2pips.py is an older script, and you found a latent bug in it
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<clay_1>
litghost oh, I see, has it been replaced by another script ?
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<litghost>
clay_1: fasm2pips is just a debugging script. fasm2bels is the more complete version
<litghost>
clay_1: You are welcome to submit a patch fixing the bug
<clay_1>
@litghost Thanks for the reply, sadly I doubt I have the skills to fix it
<clay_1>
Is fasm_pprint.py an older script that is not used anymore as well ?
<clay_1>
because I think it is missing a `from prjxray import util` line
<litghost>
clay_1: Yes
<clay_1>
litghost so there is no point in reporting it as an issue, right ?
<litghost>
clay_1: They are worth fixing, but they aren't the primary utilities
<litghost>
clay_1: bit2fasm, fasm2frames, fasm2bels are all primary utilities, the others are smaller tools that have less testing and may go stale
<clay_1>
litghost Okey, fasm2bels, is not in the project xray repo, right ?
<litghost>
clay_1: Correct
<clay_1>
so I will need to get the symbiflow repo as well
<clay_1>
litghost fasm2bels, needs --connection_database and --db_root arguments among others
<clay_1>
so for --db_root I guess it will be something like prjxray/database/artix7/xc7a35tcpg236-1 for the xc7a35tcpg236-1 part
<clay_1>
but what about the --connection_database ?
<litghost>
clay_1: I recommend letting the build system take care of that
<litghost>
clay_1: Follow the readme for examples
<clay_1>
litghost I got that info from the readme
<clay_1>
Invoking--------`python3 -mfasm2bels <options> <verilog> <tcl>`Required arguments are: - `--connection_database` - Path to connection database for part - `--db_root` - Path to prjxray database for part - `--part` - FPGA part - `--fasm_file` - Path to FASM file to process - verilog - Path to verilog file to write - tcl - Path to TCL file to write
<clay_1>
litghost if I replace the file top.bit.fasm with a .fasm file I create from bit2fasm.py and then delete the top_bit.v and top_bit.v.tcl will it efectively recreate them from the fasm file I inputed ?
<litghost>
That would work, but is kind of round-about way to do it
<litghost>
But yes
<clay_1>
yeah I am trying to find a way to make it work, in the fasm2bel line a lot of things are beeing defined
<clay_1>
what confuses me a bit is the folder title `-xc7a50t-basys3`
<clay_1>
while in the comands I see `--part xc7a35tcpg236-1`
<clay_1>
so do the 35t and 50t basys 3 have actually the same files or something like that ?
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<litghost>
All Yes
<litghost>
Yes
<clay_1>
nice, thanks for the clarification :)
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<HEGAZY>
Hi all,
<HEGAZY>
I've been lurking around the project and this IRC channel log for a couple of days now till i got the grasp for what's going on, I'm interested in joining you this year in Gsoc, I am a 4th year electronics Engineering student.
<HEGAZY>
I was an intern at mentor graphics last November worked on writing VHDL, Verilog, systemverilog testcases for the new checks in Questa lint tool, basically like what's happening in the sv-tests repo, plus validating them against customer designs like arm, amd, riscv etc and automating this using scripts
<HEGAZY>
I have implemented AES encryption in verilog and wrote a testbench for it using UVM : github.com/ahegazy/aes
<HEGAZY>
my github has multiple HDL projects that i created and other projects too, take a look if you have time: https://github.com/ahegazy?tab=repositories , this is my linkedin: linkedin.com/in/ahegazi/ (would be love to connect you guys there).
<HEGAZY>
I've checked the ideas repo but i am a bit lost, and I wanted a challenging task to learn something new, unfortunalty i don't have access to an FPGA to help in the bitstream mapping part.
<HEGAZY>
I was thinking of continuing the work on the sv-test repo (writing sv testcases from the lrm) in parrallel with a new challenging task for me, i need your input on this, what part of the project you need help most and where my experience can fit in the most?
<HEGAZY>
** TL;DR **
<HEGAZY>
* I am fascinated by the project and the amount of collaboration in it.
<tpb>
Title: AhmadHegazyResume.pdf - Google Drive (at drive.google.com)
<HEGAZY>
* need help choosing a project to work on
<HEGAZY>
Thanks :D
<ZirconiumX>
Hi HEGAZY
<ZirconiumX>
You have quite the impressive resume
<HEGAZY>
thanks ZirconiumX, hope I can learn more contributing to this project
<ZirconiumX>
So, you don't need an FPGA to help with the bitstream tools
<ZirconiumX>
But then you don't need to work on the bitstream stuff either
<HEGAZY>
yeah i am a bit lost on where i can fit the most if you can help :D
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<ZirconiumX>
Hmm. Where in the flow would you like to work? This seems like an important question to ask.
<sf-slack>
<mgielda> hi Hegazy, I believe we will be able to help you choose a project.
<sf-slack>
<mgielda> happy to see the sv-tests work. this is mostly our doing and expanding it is welcome
<sf-slack>
<mgielda> there is an ongoing effort to improve sv support in open tooling and every little bit helps
<HEGAZY>
@ZirconiumX well the whole thing is just awesome, at first i was looking for some HDL challenge, like timing analysis, CDC, i haven't got my hands dirty in those topics, but i saw the project and the work on the tools, and i didn't know what should i focus on right now
<sf-slack>
<mgielda> rule #1 focus on what you like doing most
<tpb>
Title: SymbiFlow - the GCC of FPGAs (at symbiflow.github.io)
<HEGAZY>
Hi mgielda, thanks i will help as i could, yup 1st thing i read about a week ago, that's how i got here, i will reread it again now
<sf-slack>
<mgielda> I can see that you work in QA - do you think this is what you'd like to focus on, i.e. write more tests
<sf-slack>
<mgielda> or are you longing for a more development oriented tasks? ;)
<sf-slack>
<mgielda> how do you feel with Python? c++?
<HEGAZY>
yeah the QA work was my intern at mentor, honestly I am looking for a more challenging development oriented tasks, and i can help with the testcases too,
<HEGAZY>
yeah it would be good to work with python and C++, i started off with a little contribution PR #687 in sv-tests :D
<sf-slack>
<mgielda> we will take a look, I am sure the team will chat you up tomorrow to help you figure out how to best use your talents!
<HEGAZY>
I have a small question, is there any pure HDL related work other than sv-tests?
<HEGAZY>
Great thanks mgielda
<ZirconiumX>
Yosys could always use additional testing
<sf-slack>
<mgielda> there should be. just a matter of a well defined enough task you could take on
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<clay_1>
litghost looks like the trick didnt work. top.bit.fasm gets overwritten when re-executing `make dram_test_64x1d_bit_v`
<sf-slack>
<acomodi> clay_1: try to replace the top.bit file with your bitstream instead. Fasm2bels works in a way that it dumps the fasm of the top.bit into top.bit.fasm, that is why it got overwritten
<clay_1>
thanks! will try it
<ZirconiumX>
HEGAZY: to me there are a bunch of things to do in Yosys, but I don't know if you care much about that part of the flow
<ZirconiumX>
For example, I feel like much of Yosys could opportunistically work in parallel across module
<HEGAZY>
/join #yosys
<HEGAZY>
yup that was wrong
<HEGAZY>
ZirconiumX yeah that looks intersting, but right now i don't have a clue how it works from inside :D, i'll be reading its docs and clifford paper these next days to get a better understanding of the problem thanks
<ZirconiumX>
Claire.
<ZirconiumX>
Not Clifford.
<clay_1>
I think that not all the documentation is updated on that matter yet ZirconiumX
<ZirconiumX>
True, but where you see "Clifford" use "Claire"
<ZirconiumX>
Mmm. Given that has a 2013 date, it's likely to be pretty heavily out of date I think
<mithro>
HEGAZY: Thank you for the pull request on sv-tests!
<clay_1>
True, but I guess there will be a period of people making that misstake untill it settles. Also I am not sure what applies on referencing her work on official documents (since there might be conflict of names due to lack of update)
<HEGAZY>
mithro: you'r welcome, I hope it won't be the last
<mithro>
HEGAZY: If you have interest in sv-tests and related projects, there is plenty that could be done there as part of GSoC
<ZirconiumX>
clay_1: I'd definitely avoid deadnaming people even if the paper is published under an old name.
<HEGAZY>
can you illustrate more please
<HEGAZY>
or give an example
<ZirconiumX>
To whom are you replying?
<HEGAZY>
mithro
<clay_1>
ZirconiumX I totally agree with that. I think that the best course of action is that if one plans to reference her and cant find a correct ref to directly come in contact with her and see if she can manually change that or something
<mithro>
I believe Claire has requested to be cited as "C. Wolf" if possible -- which covers both cases
<ZirconiumX>
Yeah.
<clay_1>
@mithro clever ;)
<mithro>
HEGAZY: For example, we would love to work on a "system verilog feature detector" which is able to give you a list of the system verilog functionality a project is using and thus which tools will are more likely to be compatible with the project
<HEGAZY>
do you mean features like structs, classes, functions, conditions, loops etc or am i getting it wrong?
<mithro>
HEGAZY: yeah
<mithro>
HEGAZY: Adding more complex test cases to sv-tests which check things like simulation and synthesis actually work (rather than just parsing) would be another interesting project
<mithro>
HEGAZY: My main question for you is -- what are *you* excited about working on?
<mithro>
HEGAZY: being self motivated is an important part of being a GSoC student
<mithro>
bblr
<ZirconiumX>
I've considered entering GSoC, but I have pretty terrible focus...
<HEGAZY>
mithro: honstley i am a bit confused, too many options means more confusion for me :D
<HEGAZY>
and everything is exciting, i know that if i started on one thing my whole focus will be on it, but the problem is choosing that thing
<ZirconiumX>
Adding SV tests does seem like a useful thing
<HEGAZY>
anyway i'll read more on the projects you mentioned and comeback to you
<HEGAZY>
ZirconiumX: yeah i was thinking of it as a side contribution besides the main challenge
<ZirconiumX>
I wouldn't underestimate the complexity of it :P
<HEGAZY>
yeah i know i worked kinda full time on adding testcases but i wanna improve my experience in something new
<HEGAZY>
tbh i haven't considered software development seriously till i talked to you, it looks fun and challenging for me, and i think i do quite well on it
<ZirconiumX>
I actually came to hardware from software, rather than the other way round
<ZirconiumX>
And the software stack is what gets us to the bitstream at all :P
<HEGAZY>
my major is electronics so we are more focused on hardware, but i practiced with mircocontroller and stuff with C which is software dev.
<HEGAZY>
i didn't get the last message, software stack gets you to the bitstream how?
<sf-slack>
<aryap> hello again. are artix7 and zynq7 in the symbiflow-arch-defs repo the most advanced commercial-like architecture models available?
<clay_1>
HEGAZY all the tools that do the bitstream reverse engineering are software so i think it makes sense in that way
<clay_1>
@acomodi It worked, I mean now it doesnt get overwritten and I get an output. The wierd thing now is the output itself
<clay_1>
when I try to synthesize the verilog file I get an error
<HEGAZY>
clay_1: it's more like the chicken or the egg
<clay_1>
because signal led is defined both as an input and an output ` input [7:0] led, input rx, input tx, output [8:0] led`