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<_whitenotifier-3> [sv-tests] alainmarcel opened issue #701: Blackparrot bp_top test file list as an issue - https://git.io/Jviwn
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<yusef> Hello everyone, i want to get started with Gsoc projects on FPGA. how should i get started?
<tpb> Title: Issues · SymbiFlow/ideas · GitHub (at github.com)
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<yusef> and after selecting the ideas?
<sf-slack> <pgielda> "Proposals accepted starting on March 16, 2020" -- so starting tomorrow its possible to apply
<sf-slack> <pgielda> also read https://symbiflow.github.io/summer-of-code
<tpb> Title: SymbiFlow - the GCC of FPGAs (at symbiflow.github.io)
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<sf-slack> <yusef.iqbal44> thank you very much for your replies
<sf-slack> <yusef.iqbal44> I was wondering to work on "Support Xilinx XC9500XL CPLD series" project... and I want to contribute to it
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<ZirconiumX> yusef.iqbal44: I'm pretty sure that needs a copy of ISE
<sf-slack> <yusef.iqbal44> xilinx ise?
<ZirconiumX> Yep
<ZirconiumX> Generally Vivado doesn't support any of their CPLDs
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<sf-slack> <yusef.iqbal44> yup, you're damn right
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<Guest15918> Hi I have found that SymbiFlow has some interesting projects that I want to participate in kindly inform me where to start
<ZirconiumX> Well, there's a github repo for it
<ZirconiumX> Although you should pick a different nickname
<tpb> Title: Issues · SymbiFlow/ideas · GitHub (at github.com)
<ZirconiumX> That being said, there's a lot here that is missing
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<Alaa501> I have already red some of the projects written there and I found "Getting started with embedded RISC-V tutorial" as the most interesting.
<ZirconiumX> I mean, ecosystem work is useful
<ZirconiumX> Definitely not what I would have picked, but my opinion doesn't matter much
<Alaa501> I found it interesting thought .... what types of projects do you recommend working on
<ZirconiumX> The main area I work on is a) Intel and b) Yosys
<ZirconiumX> Because FOSS support for Intel chips is genuinely awful
<ZirconiumX> But there are a bunch of things that Yosys could use
<ZirconiumX> (IMO)
<ZirconiumX> Mostly my focus is on LUT mapping
<Alaa501> interesting topics, however now I'm most interested about the FPGA's and RISC V and want to learn more about it.
<Alaa501> although I'm a beginner level but I'm willing to learn kindly provide any related learning materials if you know any
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<ZirconiumX> Alaa501: Yosys is what produces a netlist for your FPGA; you're going nowhere without it :P
<ZirconiumX> But for RISC-V you should study the instruction set manual if you haven't already
<ZirconiumX> There's also #riscv
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<wallacejohn> Hello, I am new here and have been lurking for a few days. I am interested in getting involved with this project.
<wallacejohn> I found issue #1181 in vtr-verilog-to-routing and have converted my first script to Python 3 using 2to3 in my own fork.
<wallacejohn> Should I go ahead and submit a pull request for this single script, or convert several scripts before submitting a pull request?
<wallacejohn> This will be my first pull request, so I apologize for the basic question. Thanks!
<ZirconiumX> I think all of them should be updated to Py3 honestly
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