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<mithro>
acomodi: How goes the DDR work?
<sf-slack1>
<acomodi> @mithro: I could get through fasm2bels, obtaining a bitstream, which unfortunately didn't work. We have though the design place and routed through Vivado as well
<sf-slack1>
<acomodi> I might have an idea on why it still does not pass the memtest. The input IPAD related to the 100 MHz clock is still being routed through general interconnect instead of getting into the dedicated clock net through the CCIO pip
<sf-slack1>
<acomodi> The log in the last PR is actually pretty massive ~1.5 Gigs
<sf-slack1>
<acomodi> BTW, I also get this warning from Vivado in fasm2bels
<sf-slack1>
<acomodi> `WARNING: [DRC REQP-1580] Phase alignment: Unsupported clocking topology used for RIOI3_X43Y45_OLOGIC_X1Y46_OSERDESE2. This can result in corrupted data. The RIOI3_X43Y45_OLOGIC_X1Y46_OSERDESE2/CLK / RIOI3_X43Y45_OLOGIC_X1Y46_OSERDESE2/CLKDIV pins should be driven by the same source through the same buffer type or by a BUFIO / BUFR combination in order to have a proper phase relationship OSERDESE2. Please refer to
<sf-slack1>
the Select I/O User Guide for supported clocking topologies of the chosen INTERFACE_TYPE mode.`
<litghost>
"/tmpfs/src/github/symbiflow-arch-defs/utils/quiet_cmd.sh: line 9: 13120 Killed "$@" > $OUTPUT 2>&1"
<litghost>
So OOM?
<sf-slack1>
<acomodi> Apparently yes
<mithro>
acomodi: What is the clock path into the serdes?
<sf-slack1>
<acomodi> @mithro: The output pin of the ILOGIC, instead of going through the interface and consequently to an INT tile, follows the IOI_I2GCLK_TOP, which ends up in a HCLK_CMT tile. From there it can get into the BUFG through the dedicated net
<mithro>
acomodi: Does litghost's clock placer respect the "Table 2-1: Clock-Capable Input Placement Rules" table?
<litghost>
mithro/acomodi: I believe the answer in this case is to artificially increase the criticality of the clock net
<sf-slack1>
<acomodi> @mithro: Yes, the rules in the table are preserved
<mithro>
acomodi: A CMT must be placed in the same clock region as the clock-capable input. <-- that is the important one
<mithro>
Also -> When used as a differential clock input, the direct connection comes from the P-side of the differential input pin pair
<sf-slack1>
<acomodi> @mithro: interesting actually, the minitest produces an implementation that goes against that rule. But I believe that it actually is sth like `it is highly suggested to do so` kind of rule.
<sf-slack1>
<acomodi> What is a P-side?
<sf-slack1>
<acomodi> litghost: how to achieve the increase of criticality of a net?
<litghost>
acomodi: Initially? hack it up. Simplest answer: Provide an argument the net should have high/max criticality
<litghost>
acomodi: Good long term answer: If a net sinks at a clock port, then it should have high/max criticality
<sf-slack1>
<acomodi> @litghost Ok, I think the long term solution could be achieved in a reasonable amount of effort
<litghost>
acomodi: ok
<litghost>
The reason I was suggesting a fast path was to first verify if raising the criticality even did what we wanted
<sf-slack1>
<acomodi> @litghost I'll start with the immediate hack to
<sf-slack1>
<acomodi> @litghost Yes, in fact I want first to verify this could solve the issue