<litghost>
daveshah: One minute. I believe what you are seeing there is the tiles that are not above/below the middle of the CMT, and therefore no IOI2GCLK connection exists
<daveshah>
Thanks! I was seeing some odd behaviour and what looked at a glance like a mismatch between how nextpnr was routing things and Vivado and didn't want too spend too much time on it if there was an xray issue
<daveshah>
I can look into it some more tomorrow though
<litghost>
daveshah: So I took a look, and I think it kind of works out
<litghost>
daveshah: At a minimum the CCIO pins that are directly above and below the CMT middle are okay
<litghost>
daveshah: It is possible that the CCIO pins that 2 above and below the CMT are missing their connections
<litghost>
daveshah: I'll look into the connection database for the a7 and see
<litghost>
daveshah: In particular the line "LIOI3_TBYTESRC_X0Y19/LIOI_I2GCLK_TOP1" may mean that the node "LIOI3_X0Y21/LIOI_I2GCLK_TOP0" is not probably preserved
<daveshah>
The problematic pin was RIOI3_X43Y67 (clock input for Arty A35T)
<litghost>
daveshah: That tile is not a CCIO pin, so it lacks a IOI2GCLK wire
<daveshah>
oh, sorry, typo
<litghost>
daveshah: Only the first two IOB33M pins above and below the CMT are CCIO pins
<litghost>
daveshah: Am I missing something?
<daveshah>
I copied the reset pin instead. I meant X43Y75
<daveshah>
That's not in the list, so it should work fine
<daveshah>
I'll have more of a look tomorrow
<daveshah>
thanks for your help!
<litghost>
daveshah: So that is the first IOB33M above the CMT, so I expect it should be okay?
<litghost>
daveshah: I'll check my database and see