02:08 <mithro> daveshah: I generated a database with your DSP changes

02:17 <_whitenotifier-3> [ideas] Harvie opened issue #39: Support for cheapest FPGAs on the market - https://git.io/Jvm5Q

03:32 <mithro> https://github.com/YosysHQ/yosys/pull/1657/files

03:32 <tpb> Title: synth_xilinx: add -dsp-multonly by daveshah1 · Pull Request #1657 · YosysHQ/yosys · GitHub (at github.com)

03:33 <mithro> daveshah: It seems like support for that would be pretty easy to add in vpr

12:26 <_whitenotifier-3> [prjxray] acomodi opened issue #1214: Bottleneck in 072 and 074 fuzzers - https://git.io/JvYIM

14:35 <sf-slack1> <acomodi> litghost: given that most of the tiles are actually equal, wouldn't it be ok to just dump a smaller subset of the whole device in fuzzer 074?

14:37 <sf-slack1> <acomodi> We could for instance use an ROI that includes 1 or 2 clock regions only, this way we can include all tiles that share the name, but have some discrepancies with the wires. (e.g. https://github.com/SymbiFlow/prjxray/blob/3f0804a417666ab76251c6469c9cc69801eb501a/fuzzers/074-dump_all/reduce_tile_types.py#L135-L136)

14:37 <tpb> Title: prjxray/reduce_tile_types.py at 3f0804a417666ab76251c6469c9cc69801eb501a · SymbiFlow/prjxray · GitHub (at github.com)

17:46 <mithro> http://yibolin.com/publications/papers/FPGA_ASPDAC2020_Alawieh.pdf

17:46 <mithro> "High-Definition Routing Congestion Prediction for Large-Scale FPGAs"

17:46 <mithro> litghost: ^

17:46 <mithro> daveshah: You might also be interested in the above...

17:48 <mithro> daveshah: I'm trying to get that group to release the source code for their work

17:49 <daveshah> That would be interesting

17:51 <mithro> daveshah: Apparently the top student went to Xilinx to implement the same thing in vivado....

19:07 <mithro> litghost: 100 billion!

19:07 <litghost> mithro: Yep :)

19:08 <mithro> litghost: Also -> https://github.com/martinmoene/string-view-lite

19:08 <tpb> Title: GitHub - martinmoene/string-view-lite: string_view lite - A C++17-like string_view for C++98, C++11 and later in a single-file header-only library (at github.com)

19:09 <mithro> litghost: Dunno if it's any good or useful...

19:09 <litghost> mithro: This wasn't a string-view case

19:09 <litghost> mithro: It was a simple case of forgetting to hold a reference vs value

19:29 <mithro> litghost: the two things were unrelated

19:31 <litghost> k

19:33 <_whitenotifier-3> [vtr-verilog-to-routing] acomodi opened issue #367: VTR does not allow constrained clocks with dots in the name - https://git.io/JvY0l