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<
mangelis>
hi! i wonder if it's possible to use yosys to synthesize verilog to network of generic 3-input 1-output luts?
<
mwk>
yeah, just `synth -lut 3`
<
mwk>
except you'll get a network of LUTs + FFs, which you presumably also need to select
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philtor>
A yosys discussion has broken out on r/fpga
<
tpb>
Title: FieldProgrammable comments on FPGA development board for beginners programmable w/ floss toolchain (at old.reddit.com)
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