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<awygle>
what kind of error does `ERROR: Failed to pack flipflop 'pin_ddr2_0__dq.U$$32' with 'syn_useioff' set into IOLOGIC.` from nextpnr-ecp5 indicate?
<awygle>
like obviously there's something wrong with the pin mapping/constraints but an idea of what to look at would be very helpful if somebody has one
<tnt>
You asked for a FF to be packed in the IO block and it's unable to do that.
<awygle>
is there a way i can get more information about why it was unable to do so?
<tnt>
Not that I know.
<tnt>
Basically open the .json file, find that FF, and how it's configured and try to figure out why it wouldn't be packable.
<tnt>
Where is that design from ?
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<awygle>
i wrote it
<awygle>
it's a 4x DDR output
<awygle>
so not hugely surprising that i configur3ed it wrong
<awygle>
but i wrote it in nmigen so there's a fair bit of stuff between me and waht's actually happening
<awygle>
which is why i was hoping to get a few more pointers from nextpnr et al
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<daveshah>
Tristate registers and 4:1 aren't supported at all
<awygle>
oh. well... that's probably why then
<daveshah>
Diamomd doesn't support bidirectional 4:1 at all. nextpnr supports it based on empirical testing on a best effort basis
<awygle>
diamond has those weird primitives for memory specifically, can i use those?
<daveshah>
Yes, you have to use those
<tnt>
but you need all the DQS stuff for those.
<awygle>
and based on looking at the code nmigen doesn't automagic them
<awygle>
which makes sense i spose
<tnt>
it's not a generic 4:1
<daveshah>
The choice is basically use 2:1 IO, use 4:1 IO with nextpnr only or use 4:1 with the DQS stuff for both tools
<daveshah>
I don't know why Diamond doesn't support 4:1 bidirectional, it is possible that the hardware is subtly broken
<awygle>
i mean i am only using nextpnr
<daveshah>
I know it works well enough in nextpnr for Greg to get a HyperRAM core working though
<daveshah>
Yeah but sometimes it's useful to test in Diamond too
<awygle>
it does seem pretty dumb that diamond doesn't support generic 4:1 bidir but :shrug: i guess
<tnt>
And in nextpnr, how is the tristate controlled when using 4:1 ? is it packed ?
<daveshah>
No, it isn't
<daveshah>
From what I know of the hardware I doubt a tristate reg with 4:1 IO but I haven't tested, right now it just errors
<awygle>
so i need to do dir='-' in nmigen and manually glue the Instances of the memory primitives together, then?
<daveshah>
Afraid so
<tnt>
yeah, I guess it'd be like DDR when you only control it at clk_1x, but for DDR you can still pack it, so at least it toggles "in-sync".