clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<poztit> Hi, is Yosys can format Verilog code ? I search the Yosys manual but found nothing revelant
<poztit> like clang-format for example
<Lofty> poztit: no, Yosys cannot format Verilog code
<poztit> Lofty: ok, thank you for removing the doubt
<Sarayan> poztit: I think slang can
<Sarayan> iirc
<poztit> Yes but it's the big gun to achieve just formating ^^
<Sarayan> I don't see in which way yosys is a smaller gun :-)
<poztit> Yeh true, in fact I use apio to develop on a TinyFPGA and it use Yosys to do the synthesis, so I would like to do the much I can with the tool already install
<poztit> Sarayan: Do you use a formater for your projects ?
<Sarayan> I avoid verilog :-)
<Sarayan> I'm a nmigen fan
<Sarayan> which has python formatting
<poztit> Oh interesting !
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<Sarayan> make install doesn't install the cxxrtl headers? (or any header for the matter)
<Sarayan> ah it does, how did the compiler miss them?
<Sarayan> whitequark you are insane
<Sarayan> clang++ -c -g -Wall -std=c++17 -O3 -I/people/galibert/share/yosys/include m68k.cc
<Sarayan> m68k.cc:3191:264192: note: use -fbracket-depth=N to increase maximum nesting level
<Sarayan> m68k.cc:3191:264192: fatal error: bracket nesting level exceeded maximum of 256
<Sarayan> wow, the line is >265K chars long
<cr1901_modern> Sarayan: I pinged wq, since she's not in this room rn lol
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<modwizcode> Sarayan: How are you generating the cxxrtl source for that module
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